Method of forming a semiconductor array of floating gate...

Details Method of forming a semiconductor array of floating gate... Method of forming a semiconductor array of floating gate...

2003-04-04

2004-08-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S257000, C438S591000, C438S593000, C257S239000, C257S261000, C257S315000

Reexamination Certificate

active

06773974

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of forming strap regions to make electrical contacts with memory cells in an array of semiconductor non-volatile memory cells, and more particularly, in the preferred embodiment, to an array of floating gate memory cells of the split gate type.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
In the manufacture of memory cell arrays, it is also known to form cell elements that extend across the entire array of memory cells. For example, with an array having interlaced columns of isolation and active regions, with a plurality of memory cells in each active region, memory cell elements such as control gates, source regions, drain regions etc. can be formed to continuously extend across an entire row or column of memory cells. In order to ensure an equalized voltage on such elements for all the memory cells in the target row/column, strap regions have been used to provide multiple electrical connections along the length of continuously formed memory cell elements, so that uniform voltages are applied to all the memory cells in the affected row/column.
FIG. 1
illustrates a known strap region design. Strap region
1
is formed along side a memory cell array
2
. The memory cell array
2
includes columns of active regions
3
interlaced with columns of isolation regions
4
. Rows of memory cell pairs
5
are formed with word lines
6
and source lines
7
extending along the memory cell rows, with each pair of memory cells having two word lines
6
and sharing a single source line
7
. (Those of skill in the art will recognize that the term source and drain may be interchanged. Further, the word line is connected to the control gate of the floating gate memory cell. Thus, the term control gate or control gate line may also be used interchangeably with the term word line). Typically, the word line and the source lines are made of polysilicon or polysilicide or salicide material. Thus, pure metal lines are used to strap these lines. Strap cells
8
are formed on the control gates
6
and source lines
7
as they traverse the strap region
1
. Electrical contacts
9
a
and
9
b
are then formed onto the control gate (word) lines
6
and source lines
7
respectively by metal lines (not shown) traversing in the word line direction positioned above the array shown in FIG.
1
and electrically insulated therefrom for supplying the desired voltages to the various rows of control gates
6
and source lines
7
.
Ideally, for larger memory arrays, a plurality of strap regions are interlaced within the memory cell array (e.g. one strap region for every 128 cells in the word line direction). Preferably, the strap regions are formed simultaneously with the process steps used to make the memory cell array.
As device geometries get smaller, it is increasingly difficult to reliably form electrical connections to the strap regions
8
. The word lines
6
are very close to the source lines
7
, and get even closer with smaller device geometries. As the distance between the control gate lines
6
and source line
7
shrinks, it becomes more difficult to form contacts
9
a
and
9
b
properly. For example, just a small shift of one of the control gate line
6
contacts toward an adjacent source line
7
would result in the contact being formed over both a word line
6
and a source line
7
, thus shorting the two together. Further, there is simply no room to enlarge and separate the strap cells to increase the tolerance of the contact formation steps.
Thus, there is a need for a strap cell design, and a manufacturing method thereof, that minimizes the risk of shorting source lines
7
and word lines
6
together during the formation of the strap cells, and/or during the formation of electrical contacts connected thereto. There is also a need to form such strap cells using the same processing steps that are used to form the memory cells in the active regions.
SUMMARY OF THE INVENTION
The present invention provides a memory cell array with a strap region that minimizes the risk of shorting the source and word lines together, and maximizes the spacing of contacts in the strap region to enable further scaling of device geometries.
The present invention is an array of electrically programmable and erasable memory devices, which includes a substrate of semiconductor material having a first conductivity type, an array of memory cells formed on the substrate, a first plurality of parallel spaced apart lines of a conductive material formed over the substrate and electrically coupled to the memory cells, a second plurality of parallel spaced apart lines of a conductive material formed over the substrate and electrically connected to the memory cells, and a strap region formed on the substrate and adjacent to the memory cell array. The strap region includes first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region, a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells, second strap cells in which the second plurality of conductive material lines terminate without completely traversing across the strap region, and a second plurality of conductive metal contacts each of which is connected to one of the second plurality of conductive material lines in one of the second strap cells.
In another aspect of the present invention, an array of electrically programmable and erasable memory devices includes a substrate of semiconductor material having a first conductivity type, an array of memory cells formed on the substrate, a first plurality of parallel spaced apart lines of conductive material formed over the substrate and electrically coupled to the memory cells, a second plurality of parallel spaced apart lines of conductive material formed over the substrate and electrically connected to the memory cells, and a plurality of strap regions each formed on the substrate and disposed in an interlaced fashion between adjacent portions of the memory cell array. Each of the strap regions includes first strap cells through which the first plurality of conductive material lines traverse, wherein the first plurality of conductive material lines completely traverse across the strap region, a first plurality of conductive metal contacts each of which is connected to one of the first plurality of conductive material lines in one of the first strap cells, second strap cells in which the second plurality of conductive material lines terminate without completely traversing across the strap region, and a second plurality of conductive metal contacts each of which is connected to one of the second plurality of conductive material lines in one of th

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