Method of forming a semiconductor array of floating gate...

Details Method of forming a semiconductor array of floating gate... Method of forming a semiconductor array of floating gate...

2002-07-24

2004-06-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06743674

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of forming strap regions to make electrical contacts with memory cells in an array of semiconductor non-volatile memory cells, and more particularly, in the preferred embodiment, to an array of floating gate memory cells of the split gate type. The present invention also relates to a method of forming a logic or peripheral region on the same semiconductor substrate adjacent the memory cell array, where the structure has a simplified topography, box shaped word poly's, and logic polysilicon elements formed separately from those of the memory cells.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
In the manufacture of memory cell arrays, it is also known to form cell elements that extend across the entire array of memory cells. For example, with an array having interlaced columns of isolation and active regions, with a plurality of memory cells in each active region, memory cell elements such as control gates, source regions, drain regions etc. can be formed to continuously extend across an entire row or column of memory cells. In order to ensure an equalized voltage on such elements for all the memory cells in the target row/column, strap regions have been used to provide multiple electrical connections along the length of continuously formed memory cell elements, so that uniform voltages are applied to all the memory cells in the affected row/column.
FIG. 1
illustrates a known strap region design. Strap region
1
is formed along side a memory cell array
2
. The memory cell array
2
includes columns of active regions
3
interlaced with columns of isolation regions
4
. Rows of memory cell pairs
5
are formed with word lines
6
and source lines
7
extending along the memory cell rows, with each pair of memory cells having two word lines
6
and sharing a single source line
7
. (Those of skill in the art will recognize that the term source and drain may be interchanged. Further, the word line is connected to the control gate of the floating gate memory cell. Thus, the term control gate or control gate line may also be used interchangeably with the term word line). Typically, the word line and the source lines are made of polysilicon or polysilicide or salicide material. Thus, pure metal lines are used to strap these lines. Strap cells
8
are formed on the control gates
6
and source lines
7
as they traverse the strap region
1
. Electrical contacts
9
a
and
9
b
are then formed onto the control gate (word) lines
6
and source lines
7
respectively by metal lines (not shown) traversing in the word line direction positioned above the array shown in FIG.
1
and electrically insulated therefrom for supplying the desired voltages to the various rows of control gates
6
and source lines
7
.
Ideally, for larger memory arrays, a plurality of strap regions are interlaced within the memory cell array (e.g. one strap region for every 128 cells in the word line direction). Preferably, the strap regions are formed simultaneously with the process steps used to make the memory cell array.
As device geometries get smaller, it is increasingly difficult to reliably form electrical connections to the strap regions
8
. The word lines
6
are very close to the source lines
7
, and get even closer with smaller device geometries. As the distance between the control gate lines
6
and source line
7
shrinks, it becomes more difficult to form contacts
9
a
and
9
b
properly. For example, just a small shift of one of the control gate line
6
contacts toward an adjacent source line
7
would result in the contact being formed over both a word line
6
and a source line
7
, thus shorting the two together. Further, there is simply no room to enlarge and separate the strap cells to increase the tolerance of the contact formation steps.
One or more logic or peripheral regions are formed adjacent to the memory cell array on the same silicon substrate. Logic devices (i.e. MOS FET's, etc.) are formed in these regions to operate the memory cell array or perform logic functions related to the memory cell array. In order to form such logic devices along side the memory cell array, the topography of the resulting structure can be complex, resulting in the formation of unwanted layers and spacers that are difficult to remove once the structure formation is complete. Further, certain elements of the logic devices and memory cells are often formed with the same processing steps, thus coupling the formation of these elements together. This can make it difficult to optimize elements of the logic devices without adversely affecting elements of the memory cells, and vice versa.
Thus, there is a need for a strap cell design, and a manufacturing method thereof, that minimizes the risk of shorting source lines
7
and word lines
6
together during the formation of the strap cells, and/or during the formation of electrical contacts connected thereto. There is also a need to form such strap cells using the same processing steps that are used to form the memory cells in the active regions. Further, there is a need to form a logic/peripheral region adjacent the memory cell array where the structure has a simplified topography, box shaped word line poly's, and logic poly's formed separately from those in the memory cells.
SUMMARY OF THE INVENTION
The present invention provides a memory cell array with a strap region that minimizes the risk of shorting the source and word lines together, maximizes the spacing of contacts in the strap region to enable further scaling of device geometries, and provides for logic devices formed in a decoupled manner and in a manner such that the structure has a simplified topography.
The method of the present invention includes the steps of forming a plurality of memory cells in a memory portion of a semiconductor substrate, forming a layer of protective material over control gates of the memory cells, forming a plurality of logic devices that includes forming residual conductive material on the layer of protective material, and removing the residual conductive material. The formation of each of the memory cells includes the steps of forming a floating gate of conductive material disposed over and insulated from the memory portion of the substrate, and forming a control gate of conductive material disposed over and insulated from the memory portion of the substrate. The layer of protective material is formed over the control gates. The plurality of logic devices are formed in a peripheral region of the semiconductor substrate after the formation of the protective material layer. The formation of each of the logic devices includes the step of forming a block of conductive material disposed over and insulated from the peripheral region of the substrate. The formation of the blocks of conductive material includ

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