Method of forming a semiconductor arrangement with reduced...

Details Method of forming a semiconductor arrangement with reduced... Method of forming a semiconductor arrangement with reduced...

2007-05-29

2007-05-29

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S692000, C257SE21304, C257SE21550, C257SE21546

Reexamination Certificate

active

11053910

ABSTRACT:
A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

REFERENCES:
patent: 5731241 (1998-03-01), Jang et al.
patent: 5885883 (1999-03-01), Park et al.
patent: 6027982 (2000-02-01), Peidous et al.
patent: 6251746 (2001-06-01), Hong et al.
patent: 6413828 (2002-07-01), Lam
patent: 6642124 (2003-11-01), Yamauchi
patent: 6713780 (2004-03-01), Lam
patent: 6987064 (2006-01-01), Chuang et al.

Affiliated with

Also associated with

Rating

Method of forming a semiconductor arrangement with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a semiconductor arrangement with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a semiconductor arrangement with reduced... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3813765