Method of forming a self-aligned floating gate in flash...

Details Method of forming a self-aligned floating gate in flash... Method of forming a self-aligned floating gate in flash...

2002-11-27

2003-12-02

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S259000, C257S314000

Reexamination Certificate

active

06656793

ABSTRACT:

BACKGROUND
1. Technical Field
A method of forming a self-aligned floating gate in a flash memory cell is disclosed. More specifically, a method of forming a trench insulating film is disclosed which is capable of preventing formation of a moat that is generated when the self-aligned floating gate is formed in the flash memory cell.
2. Description of the Related Art
Generally, a flash memory cell is fabricated using shallow trench isolation (STI) as a device isolation process. During the process of isolating a floating gate using a mask patterning, wafer uniformity is poor because of variations in the critical dimension (CD). It is thus difficult to implement a uniform floating gate. Further, there are problems such as program and erase fail of the memory cell, or the like, as a result of variations in the coupling ratio. In addition, when a space of below 0.13 &mgr;m is implemented in a highly-integrated design, the mask process is made more difficult. Thus, the process of manufacturing the flash memory cell serving as an important factor in implementing a uniform floating gate is made more difficult.
Due to the above reasons, if the floating gate is not uniformly formed, differences in the coupling ratio can be severe. Thus, upon program and erase of the memory cell, there is a possibility that an over erase problem may occur. This adversely affects the operational characteristics of the device. Also, the yield of the product is lowered and the cost is increased due to increased costs and lower yields of the mask process. In addition, failure of the device, or the like occurs due to a moat that is generated in STI and deep trench isolation (DTI) or nitride-spacer local oxidation of silicon (NS-LOCOS) process. In a highly-integrated flash device, it is important to increase the coupling ratio by securing a cell in which a moat does not occur.
SUMMARY OF THE DISCLOSURE
Methods are disclosed which prevent generation of a moat in a trench insulating film and to minimize spacing of a floating gate to be formed in a subsequent process, in such a way that a capping layer is formed on the trench insulating film and a cleaning process is then performed to etch the trench insulating film to a desired dimension.
Further, the disclosed method improves the coupling ratio between the floating gate and the control gate which will be formed in a subsequent process, by forming a capping layer on a trench insulating film in order to increase the height of the trench insulating film.
A disclosed method of forming a self-aligned floating gate in a flash memory cell comprises: forming a trench in a semiconductor substrate; forming a trench insulating film having a first protrusion at a portion of the trench, the first protrusion has a first width and a first height; forming a capping layer on the entire structure including the first protrusion; forming a second protrusion of the trench insulating film by etching the capping layer and a portion of the first protrusion, the second protrusion has a second width and a second height, the second width is narrower than the first width and the second height is lower than the first height; and forming a floating gate isolated by the second protrusion of the trench insulating film.
Also, a disclosed method of forming a self-aligned floating gate in a flash memory cell comprises: forming a pad oxide film and a pad nitride on a semiconductor substrate; forming a trench in the semiconductor substrate by etch a portion of the semiconductor substrate including the pad nitride film and the pad oxide film; forming a sacrifice oxide film on an internal surface of the trench; removing the sacrifice oxide film; forming a wall oxide film on the internal surface of the trench removed the sacrifice oxide film; forming a liner oxide film on the entire structure including the wall oxide film; forming a trench insulating film on the liner oxide film including the trench; forming a first protrusion of the trench insulating film at the trench by performing a chemical mechanical polishing process and removing the pad nitride film, the first protrusion has a first width and a first height; forming a capping layer on the entire structure including the first protrusion; forming a second protrusion of the trench insulating film by etching the capping layer and a portion of the first protrusion, the second protrusion has a second width and a second height, the second width is narrower than the first width and the second height is lower than the first height; forming a tunnel oxide film and a floating gate isolated by the second protrusion of the trench insulating film; removing the second protrusion of trench insulating film; and forming a dielectric film and a control gate.


REFERENCES:
patent: 4385975 (1983-05-01), Chu et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 2003/0100157 (2003-05-01), Hsu

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