Method of forming a self-aligned damage-free buried contact

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438641, 438682, H01L 218234, H01L 218244, H01L 214763, H01L 2144

Patent

active

059565853

ABSTRACT:
A method of manufacturing a semiconductor cell comprises a step of anisotropically dry etching a polysilicon layer to form a polysilicon gate wherein an etching stop is formed on a buried contact region before the anisotropically dry etching step, the etching stop is preferably formed by salicide technology of titanium silicide.

REFERENCES:
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5652160 (1997-07-01), Lin et al.
patent: 5672901 (1997-09-01), Abernathey et al.

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