Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-10
2004-08-17
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S637000
Reexamination Certificate
active
06777294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a select line in a NAND type flash memory device, and more particularly, to a method of forming a select line in a NAND type flash memory device capable of preventing degradation in electrical characteristics due to voltage drop when the bias is applied to a polysilicon layer for a floating gate having a high resistance, in the select transistors having the same structure to the flash memory cells.
2. Background of the Related Art
A NAND type flash memory of a stack structure operates in a block unit. At this time, the blocks are divided and selected, using the select transistor.
FIG. 1
is a layout view of a conventional NAND type flash memory array,
FIG. 2
is a cross-sectional view of the memory array taken along lines A-A′ in
FIG. 1
, and
FIG. 3
is a cross-sectional view of the memory array taken along lines B-B′ in FIG.
1
.
Referring to
FIG. 1
, FIG.
2
and
FIG. 3
, device isolation films
102
are formed at the semiconductor substrate
101
to define a plurality of active regions ACT that are parallel one another. Further, drain select lines DSL
0
, DSL
1
, . . . , first~n
th
word lines WL
1
~WLn and source select lines SSL
1
, SSL
2
, . . . are formed vertically to the active region ACT on the semiconductor substrate
101
. The lines have a stack structure of a tunnel oxide film
103
, a floating gate
104
, a dielectric film
105
and a control gate
106
. The control gate
106
has a stack structure of a polysilicon layer and a silicide layer. Meanwhile, impurity regions
107
d
,
107
and
107
c
are formed at the active region ACT between the drain select lines DSL
0
, DSL
1
, . . . , the first~n
th
word lines WL
1
~WLn and the source select lines SSL
1
, SSL
2
, . . . . At this time, the impurity region
107
d
formed at the edge of the drain select line DSL
1
on the opposite side of the first word line WL
1
serves as the drain. The impurity region
107
c
formed at the edge of the source select line SSL
1
on the opposite side of the n
th
word line WLn functions as the source.
Meanwhile, a drain select transistor Td is formed at a region where the drain select line DSL
1
and the active regions ACT intersect. A ground select transistor Ts is formed at a region where the source select line SSL
1
and the active regions ACT intersect. Likewise, flash memory cells Cell
1
~Celln are formed at a region where the first~n
th
word lines WL
1
~WLn and the active regions ACT intersect. At this time, the active region ACT is isolated by the isolation film
102
. However, in order to easily connect the active regions ACT between the ground select transistors Ts using the ground terminals, the active regions ACT may be formed so that the active regions ACT between the ground select transistors Ts may be connected (it is shown in the drawing that they are isolated one another). Thereby, a block B
100
having the drain select transistor Td, a plurality of flash memory cells Cell
1
~Celln and a ground select transistor Ts, all of which are serially connected to the active region ACT, is formed on the semiconductor substrate
101
.
In the above, the floating gates
103
of the flash memory cells Cell
1
~Celln are isolated one another on the device isolation region by means of the floating gate isolation FGI pattern. However, the drain select lines DSL
0
, DSL
1
, . . . and the ground select lines SSL
1
, SSL
2
, . . . are not isolated even on the device isolation film
102
but all the layers
102
~
106
are consecutively connected, as shown in FIG.
3
.
At this time, as the drain select transistor Td and the source select transistor Ts are formed to have the structure of the flash memory cell, it is required that a high voltage be applied to the select line DSL or SSL or the floating gate in order to obtain the normal transistor operation, or the dielectric films
105
between the control gate
106
and the floating gate
104
in the drain select lines DSL
0
, DSL
1
, . . . and the source select lines SSL
1
, SSL
2
, . . . be removed.
In this case, abrupt voltage drop occurs due to high resistance of the floating gate. Further, as the degree of integration in the device becomes higher, it is difficult to remove the process margin for removing the dielectric films
105
between the control gate
106
and the floating gate
104
in the drain select lines DSL
0
, DSL
1
, . . . and the source select lines SSL
1
, SSL
2
, . . . . Due to this, there is a disadvantage that the degree of difficulty in the entire processes becomes higher.
SUMMARY OF THE INVENTION
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art, and an object of the present invention is to provide a method of forming a select line in a NAND type flash memory device capable of improving electrical characteristics by minimizing generation of voltage drop, and simplifying the process steps by obviating the process of removing the dielectric film for electrically connecting the floating gate and the control gate.
In order to accomplish the above object, in the select line having the stack structure of the floating gate, the dielectric film and the control gate, the control gate is patterned so that a first projection is formed at the edge of the control gate and the floating gate is formed by means of the self-aligned etch process. At this time, the floating gate is patterned so that a second projection the one end of which overlaps the first projection is formed at the edge of the floating gate. The first and second projections are then electrically connected using the contact plugs and the metal line, whereby a voltage is simultaneously applied to the control gate of a low resistance and the floating gate of a high resistance.
In a preferred embodiment, a method of forming the select line of NAND type flash memory devices according to the present invention is characterized in that it comprises the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate in which an isolation film is formed, and then performing a first patterning process in the direction of bit lines, forming a dielectric film, a second polysilicon layer and a silicide layer on the entire structure, performing a second patterning process for the silicide layer and the second polysilicon layer so that the first projection is formed at the edge of the silicide layer and the second polysilicon layer on the device isolation region between drain select line regions, performing a third patterning process for the dielectric film and the first polysilicon layer to form drain select lines so that a second projection the one end of which overlaps the first projection is formed at the edge of the first polysilicon layer on the device isolation region between the drain select lines, forming an interlayer insulating film on the entire structure and then forming a contact hole through which the first and second projections are opened, and burying the contact hole with a conductive material to form contact plugs and also forming a metal line connecting the contact plugs formed on the first and second projections on the interlayer insulating film.
In the above, during the second patterning process, in the cell region, the silicide layer and the second polysilicon layer are patterned in order to form word lines.
The third patterning process is performed with the etch mask formed on the second projection so that the second projection is formed at the edge of the first polysilicon layer. During the third patterning process, in the cell region, a self-aligned etch process is performed in order to form the word lines, so that the dielectric film and the first polysilicon layer are patterned.
The method further comprises the step of forming insulating film spacers at the sidewalls of the drain select lines, before the interlayer insulating film is formed after the third patterning process.
Upon for
Booth Richard A.
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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