Method of forming a scan path network

Details Method of forming a scan path network Method of forming a scan path network

1998-06-04

2001-03-06

Nguyen, Hoa T. (Department: 2785)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

06199183

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a scan path network and a semiconductor integrated circuit having a scan path network. Scan path networks are a technique for effectively carrying out testing of the operation of semiconductor integrated circuits. This technique is described, for example, in the following technical paper.
“A method of length minimization and short path error correction for scan path”, Proceedings of the 52nd national convention of information processing society of Japan, No. 6, P27-28, 1996, Nakamura, Kobayashi, et al, “scan path line length optimization and hold time compensation techniques”, P.27-28.
In order to increase the degree of integration of a circuit, it is preferable to make a scan path (the length of the path (wiring) from a scan-in pad to a scan-out pad) short. However, if the scan path is simply made short, there is the possibility that hold time errors will occur. Therefore, in the above technical paper, after connection (the connecting of each circuit using wiring) is complete, a step is executed where hold time error verification is carried out and buffers are then inserted at prescribed places (places where hold time errors occur) on the scan path.
However, with the kind of method in this technical paper, timing verification of each circuit has to be carried out again, thereby lengthening the design period of a semiconductor integrated circuit. A scan path network forming method that shortens the design period is therefore desired.
SUMMARY OF THE INVENTION
The present invention is therefore a method of forming a scan path network for resolving the aforementioned problems. In a typical method of forming a scan path network at a semiconductor integrated circuit having a clock node supplying a clock signal, a scan-in node supplying scan data and a scan-out node for receiving scan data outputted from scan flip-flops, the following steps are carried out. A plurality of scan flip-flops are placed. Delay times taken for the clock signal supplied to the clock node to reach the scan flip-flops are calculated. Distances between the scan flip-flops are calculated. Skews between the scan flip-flops are calculated. A sum of the calculated distances and the skews is calculated. The smallest value from within this total is then decided upon. The scan flip-flops are then connected across the scan-in node and the scan-out node based on this smallest value.


REFERENCES:
patent: 5627841 (1997-05-01), Nakamura
patent: 5680406 (1997-10-01), Nakamura
patent: 5815655 (1998-09-01), Koshiyama
patent: 5928374 (1999-07-01), Shimizu et al.

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