Method of forming a recessed interconnect structure

Details Method of forming a recessed interconnect structure Method of forming a recessed interconnect structure

1996-06-05

1998-06-16

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438629, 438631, 438637, 438672, H01L 21283, H01L 21302

Patent

active

057670129

ABSTRACT:
A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.

REFERENCES:
patent: 3974517 (1976-08-01), Sanders et al.
patent: 5141896 (1992-08-01), Katoh
patent: 5187121 (1993-02-01), Cote et al.
patent: 5189506 (1993-02-01), Cronin et al.
patent: 5382545 (1995-01-01), Hong
patent: 5466636 (1995-11-01), Coonin et al.
Wolf, S., Silicon Processing for the VLSI Era, 1990, Lattice Press, vol. 2, pp. 189-206, 279-285, 1990.
IBM Technical Disclosure Bulletin entitled "Sub-Surface Local Interconnects," vol. 34, No. 12, May 1, 1992, pp. 283-285.
International Search Report for PCT/US 97/02509 dated Jul. 1, 1997.

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