Method of forming a quantum dot and a gate electrode using...

Details Method of forming a quantum dot and a gate electrode using... Method of forming a quantum dot and a gate electrode using...

2002-09-16

2004-06-29

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S783000, C438S786000, C438S962000

Reexamination Certificate

active

06756292

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
The present application claims priority from Korean Application No. 2001-0058748, filed Sep. 21, 2001, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND
1. Field of the Invention
The present invention relates to a method of forming a quantum dot and a gate electrode using the same. In particular, the present invention relates to a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode comprising the quantum dot.
2. Description of the Related Art
Recently, information media, such as computers, are widely used, so that semiconductor technology makes great strides. In a functional aspect, a semiconductor device is required to be operated at a high speed with a large storage capacitance. Accordingly, the semiconductor technology is developed to improve the integration degree, the reliability, and the response speed of the semiconductor device.
In the semiconductor memory device, the integration level of a dynamic random access memory (DRAM) has been increased year by year. Now, a 64 gigabit DRAM cell having about a 70 nm design rule is expected to be manufactured by 2008, and a 1 terabit DRAM cell having about a 35 nm design rule is expected to be manufactured by 2014.
However, the conventional method of forming a layer, for example including an optical lithography technique and a chemical vapor deposition (CVD) technique, is not proper to manufacture the 64 gigabit DRAM cell or 1 terabit DRAM cell, so that research on an improved method of manufacturing the high density DRAM cell has been carried out intensively.
A new lithography technique using an electron beam (EB) or X-ray has been developed in substitute for the optical lithography technique, and an atomic layer deposition (ALD) technique has superseded the CVD technique. In addition, a semiconductor device is now feverishly under study, including a quantum dot of nanometric size which can be applicable to a single electron gate.
A semiconductor device including the quantum dot and a manufacturing method for the semiconductor device using the same are disclosed in U.S. Pat. No. 6,060,743 (issued to Sugiyama et al.), U.S. Pat. No. 6,090,666 (issued to Ueda et al.), and U.S. Pat. No. 6,118,686 (issued to Taira et al.).
The quantum dot has been mainly formed by the following methods.
The quantum dot can be formed using a focused ion beam (FIB), or the EB. The FIB or the EB can coercively put ions or atoms into a predetermined region of the semiconductor substrate, and advantageously, the FIB or the EB can easily control the size and the position of the quantum dot. However, the method of forming the quantum dot using the FIB or the EB has a low productivity, so that the method is not suitable for commercial applications.
The quantum dot can also be formed by forming nuclear atoms as disclosed in the U.S. Pat. No. 6,090,666. In detail, a non-crystalline layer having an amorphous substance is first formed, and then the non-crystalline layer is thermally processed to form a mono crystal. The method disclosed in the U.S. Pat. No. 6,090,666 forms the quantum dot by using the mono crystal. The method using the mono crystal has advantageously a high productivity, but the size and the distribution of the quantum dot is hard to control.
Accordingly, a new method is required to form the quantum dot in such a manner that the size and distribution of the quantum dot are easily controlled and the productivity of the quantum dot is high enough to have a good commercial use.
SUMMARY
The present invention has been made to solve the above problems of the related art, therefore, it is a first object of the present invention to provide a method for forming a quantum dot capable of easily controlling the size and the position of the quantum dot and having a high productivity.
A second object of the present invention is to provide a method for forming a gate electrode of the semiconductor device using the above method for forming the quantum dot.
In one aspect of the present invention, there is provided a method of forming a quantum dot comprising: i) depositing a first layer including a first material on a substrate, the first material having first atoms which are superabundantly present and bound with a weak bonding energy in the first layer; ii) depositing a second layer including a second material on the first layer, the second material having second atoms capable of migrating into the first layer; and iii) allowing the first atoms to migrate to the second layer, and the second atoms to migrate from the second layer to the first layer to arrange the second atoms in the first layer.
In detail, a quantum dot may be formed by: i) depositing a SiON (silicon oxide nitride) layer including Si atoms on a substrate, the Si atoms being superabundantly present therein and bound with a weak bonding energy in the SiON layer; ii) depositing a conductive layer including a conductive material on the SiON layer, the conductive material having reaction atoms capable of migrating into the SiON layer; and iii) performing a heat treatment to migrate the reaction atoms from the conductive layer into the SiON layer, whereby the reaction atoms are arranged in the SiON layer.
In another aspect of the present invention, there is provided a first method of forming a gate electrode in a semiconductor device comprising: i) defining a substrate into an active area and a field area; ii) depositing a gate oxide layer on the active area of the substrate; iii) depositing a SiON layer including Si atoms on the gate oxide layer, the Si atoms being superabundantly present therein and bound with weak bonding energy in the SiON layer; iv) depositing a conductive layer including a conductive material on the SiON layer, the conductive material having reaction atoms capable of migrating into the SiON layer; v) performing a heat treatment to allow the reaction atoms to migrate from the conductive layer to the SiON layer, whereby the reaction atoms are arranged in the SiON layer to form the reaction atoms into a quantum dot; vi) removing the conductive layer to expose a surface of the SiON layer; vii) depositing an electrode layer including a gate electrode material on the SiON layer; and viii) sequentially etching the electrode layer and the SiON layer of a predetermined region to expose a surface of the gate oxide layer.
In yet another aspect of the present invention, there is provided a second method for forming a gate electrode in a semiconductor device comprising: i) defining a substrate into an active area and a field area; ii) depositing a gate oxide layer on the active area of the substrate; iii) depositing a SiON layer including Si atoms on the gate oxide layer, the Si atoms being superabundantly present therein and bound with weak bonding energy in the SiON layer; iv) etching the SiON layer of a predetermined region to form a SiON pattern layer partially exposing a surface of the gate oxide layer; v) successively depositing a conductive layer including a conductive material on the SiON pattern layer and the gate oxide layer, the conductive material having reaction atoms capable of migrating into the SiON layer; vi) performing a heat treatment to allow the reactant atoms to migrate from the conductive layer to the SiON layer, whereby the reaction atoms are arranged in the SiON layer to form the reaction atoms into a quantum dot; vii) removing the conductive layer to expose a surface of the SiON pattern layer and the gate oxide layer; and viii) depositing an electrode layer including a gate electrode material on the SiON pattern layer.
In still another aspect of the present invention, there is provided a third method for forming a gate electrode in a semiconductor device comprising: i) defining a substrate into an active area and a field area; ii) depositing a gate oxide layer on the active area of the substrate; iii) depositing a SiON layer including Si atoms on the gate oxide layer, the Si atoms being superabundantly present ther

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