Method of forming a pattern using a photoresist without...

Details Method of forming a pattern using a photoresist without... Method of forming a pattern using a photoresist without...

2001-12-21

2004-01-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S725000, C430S317000, C430S330000, C430S190000

Reexamination Certificate

active

06673706

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a pattern in the manufacturing of a semiconductor device. More particularly, the present invention relates to a method of using photoresist to form an electronics pattern of a semiconductor device.
2. Description of the Related Art
When manufacturing a DRAM, in order to minimize gate resistance and attain the optimum refresh time it is necessary to selectively silicidate the gates. In this case, the silicide layer should not be formed on the active area.
Lately, a merged DRAM with logic (MDL) has been recognized for its high performance and small chip size. When manufacturing an MDL, silicide is formed on both an active area and on gates, or on parts of the active area and gates in a peripheral circuit and logic portion of the MDL, in order to reduce contact resistance or sheet resistance of the gates and source/drain. On the other hand, the silicide is selectively formed on the gates of a memory cell array portion in order to attain the optimum refresh time.
In the case of manufacturing a SRAM, suicide is selectively formed on the active area and on all of the gates in order to attain a high-speed operation.
In the case of an NVM, the greater the pattern density, the longer the gate must be. Therefore, silicide has only recently begun being selectively formed on the gates of NVMs in order to reduce resistance.
Techniques of silicidating a selected area in the manufacturing of a semiconductor device is disclosed in Korean Patent Laid-Open Publication No. 2000-000885 and Japanese Patent Laid-Open Publication No. Hei 11-163326.
The technique disclosed in Korean Patent Laid-Open Publication No. 2000-000885 will be described with reference to the flow chart of FIG.
1
and the sectional views of
FIGS. 2 through 8
.
First, a plurality of gates
12
including side wall spacers
11
are formed on a substrate
10
. Then, a target layer to be patterned, for example, a silicidation blocking dielectric layer
14
, is formed over the entire surface of the substrate
10
, and an anti-reflection layer
16
is formed on the silicidation blocking dielectric layer
14
(step
1
), as shown in FIG.
2
. Next, in step
2
, a photoresist coating
20
is formed on the anti-reflection layer
16
, as shown in FIG.
3
. In step
3
and as shown in
FIG. 4
, an exposure process is performed using a mask
30
having a transmission area corresponding to an upper portion of the gates
12
that are to be subjected to silicidation. In step
4
and as shown in
FIG. 5
, the exposed portion of the photoresist
20
is removed using a general developing solution, whereby a photoresist pattern
20
P is formed. The photoresist pattern
20
P exposes areas directly above the gates
12
. In step
5
, portions of the anti-reflection layer
16
and the silicidation blocking dielectric layer
14
are removed using the photoresist pattern
20
P as an etching mask, whereupon the upper portions of the gates
12
are exposed as shown in FIG.
6
. Then, in step
6
, the photoresist pattern
20
P and the remainder of the anti-reflection layer
16
are removed, as shown in FIG.
7
. Finally, in step
7
, a silicidation process is performed in which a silicide layer
40
is formed on the upper portion of the gates
12
, as shown in FIG.
8
.
However, this prior art process is complicated because it requires the forming of the anti-reflection layer
16
to prevent irregular reflection at the surface of the silicidation blocking dielectric layer
14
, and the removing of the anti-reflection layer
16
after the patterning process. Also, the smaller the gates
12
and the greater their density, the more likely a misalignment error will occur during the exposure process. When such a misalignment error occurs, the silicide layer is not formed locally on the upper portion of the gates
12
or an undesirable silicide layer is formed locally on an active area.
Also, according to the prior art method disclosed in Korean Patent Laid-Open Publication No. 2000-000885, the entire surface of the substrate is coated with undoped silicate glass (USG). Subsequently, the USG layer is etched back using a microloading effect. As a result, the USG layer remains in the memory cell array portion where the gate patterns are dense, whereas the USG layer is almost etched in the peripheral circuit and logic portion where gate patterns are sparse. However, when the USG layer is etched back, the remaining USG layer is not uniform, and the selectivity of the process to an etch-back stopper of a lower portion of the USG layer and the silicidation blocking dielectric layer is low. Therefore, the process is marked by poor stability and reproducibility. Also, it becomes impossible to achieve partial silicidation of the peripheral circuit and logic portion.
Japanese Patent Laid-Open Publication No. Hei 11-163326 discloses methods of forming a semiconductor device having a memory cell array portion (region A) and a logic portion (region B). In one embodiment, as shown in
FIG. 9
, a silicidation blocking dielectric layer
14
and photoresist
20
are sequentially formed over the entire surface of a substrate
10
on which gates
12
and gate side wall spacers
11
have been formed. Next, as shown in
FIG. 10
, the photoresist
20
in the peripheral circuit and logic portion (region B) is exposed using a mask
35
. The exposed photoresist
20
is developed to form a photoresist pattern
20
P that covers the memory cell array portion (region A) and exposes the peripheral circuit and logic portion (region B), as shown in FIG.
11
. The photoresist pattern
20
P is etched back to form a secondary photoresist pattern
20
P′ that exposes an upper portion of gate patterns in the memory cell array portion (region A), as shown in FIG.
12
. Next, the blocking dielectric layer
14
is etched using the secondary photoresist pattern
20
P′ as an etching mask to form a blocking dielectric layer pattern
14
P. At this stage of the method, an active area of the peripheral circuit and logic portion (region B) and an upper portion of gates
12
in the memory cell array portion (region A) are exposed, as shown in FIG.
13
. Subsequently, the secondary photoresist pattern
20
P′ is removed, as shown in
FIG. 14
, and a silicidation process is performed such that a silicide layer
40
is formed on the upper portion of the gates
12
in the memory cell array portion (region A), on the upper portion of the gates
12
in the peripheral circuit and logic portion (region B), and on the active area of the peripheral circuit and logic portion (region B), as shown in FIG.
15
.
However, this method is also complicated because of the numerous steps required, including the steps of forming a silicidation blocking dielectric layer, forming a photoresist layer, exposing the photoresist layer, developing the photoresist layer (forming a photoresist pattern), etching back the photoresist pattern, etching the blocking dielectric layer, removing the photoresist pattern, and performing silicidation. Also, it is difficult to provide a high degree of selectivity in the etch back of the photoresist pattern with respect to the blocking dielectric layer. In the case of low selectivity, the upper portion of the gates are exposed. Moreover, the etch-back process does not produce a high degree of uniformity.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to overcome the disadvantages and limitations of the prior art.
More specifically, one object of the present invention is to provide a relatively simple method of forming a pattern in the manufacturing of a semiconductor device, which is not limited by the design rule of the device.
Another object of the present invention is to provide a relatively simple silicidation method which facilitates the selective silicidation of an area(s) on a substrate and that is economical to carry out.
It is yet another object of the present invention to provide a method of forming a photoresist pattern without using an ex

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