Method of forming a passivation layer of a DRAM

Details Method of forming a passivation layer of a DRAM Method of forming a passivation layer of a DRAM

2000-01-28

2001-07-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06261891

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of forming a passivation layer of a DRAM (dynamic random access memory) on a semiconductor wafer, and more particularly, to a method of forming a silicon-oxygen-nitride passivation layer of a DRAM on a semiconductor wafer.
DESCRIPTION OF THE PRIOR ART
A self-aligned contact (SAC) etching process is a widely used technique in the field of DRAM fabrication on a semiconductor wafer. The formation of a contact hole, subsequently filled with doped polysilicon, is used as a node contact to electrically connect, for example, memory cells and bit lines of the DRAM. The SAC etching process possesses more alignment tolerance so as to ensure the reliability of the node contact. There is an excellent etching selectivity between silicon nitride and borophosphoslicate glass (BPSG), meaning that the SAC etching process can remove the BPSG faster than the silicon nitride layer. The silicon nitride layer is used as a stop layer for the SAC etching process.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are cross-sectional diagrams of forming a contact hole
23
, using a prior art SAC etching process on a semiconductor wafer
10
. The semiconductor wafer
10
comprises a silicon substrate
12
, and two adjacent gates
13
positioned on the surface of the silicon substrate
12
. Each of the gates
13
comprises a silicon oxide layer
14
, a polysilicon layer
15
and a silicide layer
16
. Each gate
13
further comprises a silicon nitride spacer
18
on each of two opposite walls, and a silicon nitride passivation layer
17
on the top surface of the gate
13
.
Before the SAC etching process is performed, a low pressure chemical vapor deposition (LPCVD) process is performed to form a silicon nitride layer
19
on the surface of the silicon substrate
12
and the gate
13
. The silicon nitride layer
19
is used as an etching stop layer. Another LPCVD process is performed to deposit a BPSG layer
20
that serves as a dielectric layer on the surface of the silicon nitride layer
19
, as shown in
FIG. 2. A
photoresist layer
21
is formed on the BPSG layer
20
and then a lithographic and an etching process are performed to form an opening
22
in the photoresist layer
21
for patterning the contact hole, as shown in
FIG. 3. A
SAC etching process is performed to remove the BPSG layer
20
under the opening
22
down to the surface of the silicon nitride layer
19
. The photoresist layer
21
and the silicon nitride layer
19
are used as etching masks, as shown in FIG.
4
. The selectivity of the etching process is then changed to remove the silicon nitride layer
19
under the opening
22
down to the surface of the silicon substrate
12
. The photoresist layer
21
is then removed to complete the contact hole
23
, as shown in FIG.
5
.
Because there is an excellent etching selectivity between the silicon nitride layer
19
and the BPSG layer
20
, the silicon nitride layer
19
is generally used as an etching stop layer for the SAC etching process. Furthermore, the silicon nitride layer
19
prevents diffusion of boron and phosphorous from the BPSG layer
20
into the gate
13
and the silicon substrate
12
. Consequently, the silicon nitride layer
19
is widely used as a diffusion barrier layer in the field of semiconductor wafer fabrication. A tensile stress, however, is generated at the interface between the silicon substrate
12
and the silicon nitride layer
19
after the deposition of the silicon nitride layer
19
. This tensile stress causes cracks in the silicon nitride layer
19
and causes electrical discharge from the capacitor of the DRAM. These cracks are a diffusion path for boron and phosphorous from the BPSG layer
20
into the silicon substrate
12
and the gate
13
. In order to overcome the electrical discharging of the capacitor, the refresh frequency of the capacitor must be increased to ensure the validity of the stored data in the DRAM.
After all of the devices on the semiconductor wafer
10
are completed, a hydrogen annealing process is performed on the semiconductor wafer
10
to erase dangling bonds at the interface between the silicon oxide layer
14
and the silicon substrate
12
. But since the silicon nitride layer
19
possesses a low permeability to hydrogen, it is difficult for hydrogen to diffuse into the interface between the silicon oxide layer
14
and the silicon substrate
12
. This reduces the efficiency of the hydrogen annealing process.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a silicon-oxygen-nitride passivation layer of a DRAM on a semiconductor wafer.
In a preferred embodiment, the present invention provides a method of forming a passivation layer of a DRAM on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, and two adjacent gates positioned on the surface of the silicon substrate, each gate comprising a spacer on each of two opposite walls, the method comprising:
forming a first silicon-oxygen-nitride layer of predetermined thickness on the semiconductor wafer wherein the first silicon-oxygen-nitride layer is used as a diffusion barrier layer;
forming a second silicon-oxygen-nitride layer of predetermined thickness on the first silicon-oxygen-nitride layer wherein the second silicon-oxygen-nitride layer is used as an etching stop layer;
forming a BPSG layer uniformly on the second silicon-oxygen-nitride to planarize the surface of the semiconductor wafer wherein the BPSG layer is used as a dielectric layer;
wherein the first silicon-oxygen-nitride layer is used to prevent diffusion of boron and phosphorous from the BPSG layer into the silicon substrate, the first and the second silicon-oxygen-nitride layers together constitute the passivation layer of the DRAM, the extinction coefficient of the first layer is smaller than that of the second layer, and the extinction coefficient of the first and the second layers is between 0.3 and 0.8.
It is an advantage of the present invention that there is less tensile stress at the interface between the silicon substrate and the passivation layer formed of silicon-oxygen-nitride so that the formation of cracks can be avoided. The silicon-oxygen-nitride layer possesses a higher permeability to hydrogen so that the efficiency of the hydrogen annealing process is enhanced, and the LPCVD process performed at a high temperature is replaced by a PECVD process performed at lower temperature so that the thermal budget is reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5547893 (1996-08-01), Sung
patent: 5567640 (1996-10-01), Tseng
patent: 5786250 (1998-07-01), Wu et al.

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