Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-02-13
2003-10-28
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S106000, C438S584000, C438S611000, C438S612000, C438S613000, C438S689000, C438S694000, C438S751000, C438S754000
Reexamination Certificate
active
06638796
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to semiconductor device fuse fabrication.
BACKGROUND OF THE INVENTION
Conventional laser fuses now used in the integrated circuit (IC) industry are typically at the metal level (N−1 or N−2) where precise intermetal dielectric (IMD) etch depth control is very difficult, but needed for successful laser repair. This is even more difficult for copper (Cu) interconnects because of damascene processing (more metal and IMD thickness variation due to chemical mechanical polishing (CMP)).
U.S. Pat. No. 6,162,686 to Huang et al. describes a method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area and in the product device areas.
U.S. Pat. No. 6,100,118 to Shih et al. describes a fuse guard ring method and structure.
U.S. Pat. No. 6,277,674 B1 to Wang et al. describes a fuse and a process for fabricating the fuse.
U.S. Pat. No. 5,914,524 to Komenaka describes a semiconductor device.
U.S. Pat. No. 4,740,485 to Sharpe-Geisler describes a method for forming a titanium tungsten fuse.
U.S. Pat. No. 4,796,075 to Whitten describes a fusible link structure for integrated circuits.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming a top-metal fuse.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.
REFERENCES:
patent: 4740485 (1988-04-01), Sharpe-Geisler
patent: 4796075 (1989-01-01), Whitten
patent: 5895262 (1999-04-01), Becker et al.
patent: 5914524 (1999-06-01), Komenaka
patent: 6004834 (1999-12-01), Tsukude et al.
patent: 6100118 (2000-08-01), Shih et al.
patent: 6162686 (2000-12-01), Huang et al.
patent: 6277674 (2001-08-01), Wang et al.
Ackerman Stephen B.
Kilday Lisa
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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