Method of forming a node contact hole on a semiconductor wafer

Details Method of forming a node contact hole on a semiconductor wafer Method of forming a node contact hole on a semiconductor wafer

1999-10-20

2001-08-21

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S253000

Reexamination Certificate

active

06277685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a contact hole, and more particularly, to a method of forming a node contact hole on a semiconductor wafer.
2. Description of the Prior Art
A memory cell of dynamic random access memory (DRAM) comprises a transistor and a capacitor that is stacked on the transistor. The transistor is used as a switch for controlling a bit line and reading the data stored in the capacitor. The electrical connection between the transistor and the bottom electrode of the capacitor is a conductor-filled node contact hole. Generally, a self-alignment contact (SAC) process is performed to form the node contact hole, which accurately defines the position of the node contact hole through the area between two bit lines.
Please refer to
FIG. 1
, FIG.
2
A and FIG.
2
B.
FIG. 1
is an overhead schematic diagram of a semiconductor wafer
10
according to the prior art.
FIG. 2A
is a cross-sectional schematic diagram along line a—a of the semiconductor wafer
10
shown in FIG.
1
.
FIG. 2B
is a cross-sectional schematic diagram along line b—b of the semiconductor wafer
10
shown in
FIG. 1. A
semiconductor wafer
10
comprises a silicon substrate
12
, a plurality of approximately square cross-sectional word lines
14
positioned on the silicon substrate
12
, a bottom dielectric layer
20
positioned on each word line
14
, a first dielectric layer
22
positioned on the bottom dielectric layer
20
, two bit lines
24
positioned on two predetermined areas of the first dielectric layer
22
, and a second dielectric layer
28
covering the first dielectric layer
22
and the two bit lines
24
. The vertical faces of each word line
14
are covered by a first spacer
16
. The vertical faces of each bit line
24
are covered by a second spacer
26
. The semiconductor wafer
10
further comprises a landing pad
18
that protrudes from the silicon substrate
12
and is inlaid between two adjacent first spacers
16
.
Please refer to
FIG. 3
, FIG.
4
A and FIG.
4
B.
FIG. 3
is an overhead schematic diagram of a photoresist layer
30
formed on the semiconductor wafer
10
shown in
FIG. 1
during a node contact hole process using a self-alignment contact technique.
FIG. 4A
is a cross-sectional schematic diagram along line c—c of the semiconductor wafer
10
shown in FIG.
3
.
FIG. 4B
is a cross-sectional schematic diagram along line d—d of the semiconductor wafer
10
shown in FIG.
3
. During a node contact hole process using a self-alignment contact technique, a lithographic process is first performed to form a photoresist layer
30
on the semiconductor wafer
10
wherein the photoresist layer
30
comprises at least one opening
32
to the second dielectric layer
28
to define the position of the node contact hole. The opening
32
is positioned between the two adjacent second spacers
26
and the two adjacent first spacers
16
. Consequently, the photoresist layer
30
for a DRAM would have a plurality of openings
32
arranged as a matrix.
Please refer to FIG.
5
A and FIG.
5
B.
FIG. 5A
is a cross-sectional schematic diagram of a node contact hole
34
formed on the semiconductor wafer
10
shown in FIG.
4
A.
FIG. 5B
is a cross-sectional schematic diagram of a node contact hole
34
formed on the semiconductor wafer
10
shown in FIG.
4
B. After the photoresist layer
30
is completed, an anisotropic dry etching process is performed. In a condition that the first spacers
16
and the second spacers
26
can't be removed, the second dielectric layer
28
and the first dielectric layer
22
under the opening
32
of the photoresist layer
30
are vertically removed so as to form a node contact hole
34
. Finally, the photoresist layer
30
is removed to complete the node contact hole process.
Please refer to FIG.
6
A and FIG.
6
B.
FIG. 6A
is a cross-sectional diagram of a bottom electrode of a capacitor formed within the node contact hole
34
shown in FIG.
5
A.
FIG. 6B
is a cross-sectional diagram of a bottom electrode of a capacitor formed within the node contact hole
34
shown in FIG.
5
B. After the node contact hole
34
is completed, a bottom electrode of a capacitor can be formed within the node contact hole
34
. First, a polysilicon layer
36
is formed on the semiconductor wafer
10
that fills the node contact hole
34
. Then, the polysilicon layer
36
positioned outside a predetermined area is removed which leaves the remaining polysilicon layer
36
inlaid with the node contact hole
34
. The bottom of the remaining polysilicon layer
36
is in contact with the landing pad
18
to electrically connect to the transistor of the semiconductor wafer
10
. The top of the remaining polysilicon layer
36
protruding from the second dielectric layer
28
is used as the bottom electrode of the capacitor.
The position of the node contact hole
34
is defined by using a self-alignment technique along the opening
32
of the photoresist layer
30
. Hence, the parameters of the lithographic process must be carefully controlled to ensure the accuracy of the position of the opening
32
, thereby ensuring the accuracy of the position of the node contact hole
34
.
As the pattern of the DRAM shrinks, the distance between two adjacent node contact holes
34
becomes shorter. Consequently, the openings
32
of the photoresist layer
30
must be formed closer to each other. However, when an exposure process is performed on this smaller pattern during the lithographic process, the resolution of the pattern is reduced because of the difficulty in controlling the exposure energy and focus length for the matrix arrangement of openings
32
. The lowered resolution will decrease the accuracy in defining the position of the opening
32
and bring about many adverse influences on the properties of the subsequently formed node contact hole
34
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a node contact hole on a semiconductor wafer that can exactly define the position of the node contact hole and ensure the accuracy of the position of the node contact hole when the distance between two node contact holes becomes smaller.
In a preferred embodiment, the present invention provides a method of forming a node contact hole on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove among the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines, the method comprising:
performing a lithographic process to form a photoresist layer on the second dielectric layer which comprises at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove;
performing an etching process along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole; and
forming a spacer by using an insulating material on the walls of the node contact hole to complete the node contact hole over which the spacer completely covers the walls of the two bit lines within the node contact hole but the surface of the silicon substrate exposed at the bottom of the node contact hole is not completely covered by the spacer.
It is an advantage of the present invention that the method of forming the node contact hole on the semiconductor wafer can ensure the accuracy of the position of the node contact hole and the accuracy won't be reduced as the pattern of the DRAM shrinks.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed descript

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