Method of forming a multi-level memory array with channel bias a

Details Method of forming a multi-level memory array with channel bias a Method of forming a multi-level memory array with channel bias a

1997-09-09

1999-12-21

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, H01L 218236

Patent

active

060048484

ABSTRACT:
A technique for storing multiple bits per cell in a read only memory device, provides for two kinds of code implants in the memory array. A shallow implant such as used in prior art mask ROMs is used for coding a first bit, and a deeper implant is used for coding a second bit in the memory cells. Furthermore, the cells are implemented in a semiconductor substrate so that the channels of the transistors in the mask ROM can be biased. The memory cells include as isolation layer formed in the semiconductor substrate, and a channel well formed in the isolation layer. The device includes resources to apply a first bias potential such as ground, to channel regions of memory cells in the array. When the first bias potential is applied through the channel regions, the memory cells have particular thresholds determined at least in part by the dope concentrations in the channel regions. The device also includes resources to apply a second bias potential to the channel regions of the memory cells. When the second bias potential is applied, a shift in the threshold voltages in the memory cells is induced. The shift in threshold voltage occurs because of the so called body effect, and will be greater in the memory cells which have the deep implants, than in the memory cells which do not have the deep implants. The device also includes wordlines and bitlines by which to read the data stored in the array.

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