Method of forming a MOS transistor of a semiconductor device

Details Method of forming a MOS transistor of a semiconductor device Method of forming a MOS transistor of a semiconductor device

2002-06-17

2004-03-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000

Reexamination Certificate

active

06699744

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The disclosure relates to a method for forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device.
2. Description of the Related Art
With the high degree of integration of semiconductor devices, the line width of electrodes has become smaller, and electrodes having a higher signal processing speed are required. Therefore, for a word line and a bit line, a polycide structure (a double structure made by forming a metal layer using tungsten silicide or tungsten on doped polysilicon) is frequently employed.
In addition, in case of a buried channel type MOS transistor having a gate with such a tungsten polycide structure, as the size becomes smaller, there is a limit to the extent to which the channel length and internal operating voltage can be reduced, due to the degradation of the characteristics of the MOS transistor, such as a shift in the threshold voltage, an increase in punch-through voltage, and substrate threshold leakage according to a short channel effect.
FIG. 1
is a cross-sectional view illustrating a MOS formed by a conventional method for forming a MOS transistor of a semiconductor device. In the conventional art, as an alternative to the method for a buried channel described above, a gate oxide film
40
is formed on a semiconductor substrate
10
having a field oxide film
20
and threshold voltage ions are then implanted.
Then, an electrode with a polycide structure is formed by depositing a conductive layer
50
on the gate oxide film
40
. Afterwards, in a process of forming a PMOS region and a NMOS region on the conductive layer
50
, a gate electrode is formed by ion-implanting P into NMOS and ion-implanting B or BF
2
into PMOS, thereby forming a surface channel.
Then, a metal layer
60
is deposited on the conductive layer
50
and, after a gate patterning etching process is conducted by coating a photoresist film (not shown) thereon, a gate pattern
70
is formed.
At this time, due to the limitation on the selectivity of etching gases used in the gate patterning etching process, the side walls of the conductive layer
50
are excessively etched and lost as shown in “A”.
Therefore, it is necessary to prevent the oxidization of the metal layer
60
of the gate pattern by conducting a high temperature heat process onto the gate pattern
70
and to compensate for the sidewalls of the conductive layer
50
lost from excessive etching by oxidizing only the conductive layer
50
.
However, the gate electrode is formed by implanting p+ ions such as B or BF
2
onto the PMOS. Thus, in the high temperature heat process, the p+ ions in the gate electrode penetrate the semiconductor substrate through a lower gate oxide film due the bad thermal stability of the p+ ions. Accordingly, there occurs a problem that the threshold voltage of the PMOS transistor changes and the driving voltage is reduced.
In addition, there is another problem in that high-doping of the p+ ions is difficult because the p+ ions in the gate electrode are diffused into an upper metal layer.
SUMMARY OF THE DISCLOSURE
The disclosure provides a method for forming a PMOS transistor of a semiconductor device that minimizes the phenomenon of a temporary reinforcement and diffusion of dopants for controlling a threshold voltage and dopants for forming a gate electrode due to selective oxidization of the side walls of a conductive layer even though a post heat process is performed at a low temperature by implanting inert ions into the entire semiconductor substrate having a gate pattern formed of a conductive layer and a metal layer, thus making the conductive layer and the metal layer have different surface binding capacities.
The disclosure provides a method of forming a MOS transistor of a semiconductor device including the steps of: ion-implanting dopant for controlling the threshold voltage after forming a gate oxide film on the semiconductor substrate having a field oxide film; forming gate electrodes of NMOS and PMOS by ion-implanting n+ and p+ ions, respectively, after forming a conductive layer on an upper portion of the gate oxide film; forming a gate pattern by performing an etching process through a photoresist film as a mask after sequentially depositing a metal layer and the photoresist film on an upper portion of the conductive layer; performing an inclination ion-implanting process of inert ion on the semiconductor substrate having the gate pattern; and compensating for a loss of the conductive layer by performing a low temperature heat process on the gate pattern implanted with the inert ion and forming a tungsten nitride film on the surface of the metal layer.
The disclosed method minimizes the phenomenon of a temporary reinforcement and diffusion of dopants for controlling a threshold voltage and dopants for forming a gate electrode due to the selective oxidization of side walls of a conductive layer even though a post heat process is performed at a low temperature by implanting inert ions into the entire semiconductor substrate having a gate pattern consisting of a conductive layer and a metal layer and thus making the conductive layer and the metal layer have different surface binding capacities.
Moreover, N
2
dopants, i.e., the implanted inert ions, remain on the surface of the metal layer and are reacted with tungsten of the upper metal layer to thus form a tungsten nitride film on the surface of the metal layer, thereby enhancing the resistance of the junction region for a post process without conducting any additional steps on the upper portion of the metal layer and as a result, reducing a number of process steps.


REFERENCES:
patent: 5308780 (1994-05-01), Chou et al.
patent: 5565700 (1996-10-01), Chou et al.
patent: 6090653 (2000-07-01), Wu
patent: 6146970 (2000-11-01), Witek et al.

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