Method of forming a MOS transistor

Details Method of forming a MOS transistor Method of forming a MOS transistor

2000-02-04

2001-10-02

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S306000, C438S307000, C438S976000

Reexamination Certificate

active

06297112

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a MOS transistor, and more particularly, to a method of forming a MOS transistor to prevent damage caused by an RCA cleaning process.
2. Description of the Prior Art
Metal oxide semiconductor (MOS) transistors are probably the most important components of semiconductor products. They are generally categorized as P-channel MOS (PMOS) transistors, N-channel MOS (NMOS) transistors or complementary MOS (CMOS) transistors. A MOS transistor comprises a gate, a drain and a source. In general, the gate is first formed on a silicon substrate of a semiconductor wafer. Then, an ion implantation process is performed, using the gate as a mask, to form a lightly doped drain (LDD), or a source and drain (S/D) on the silicon substrate around the gate. Then, a cleaning process is performed to remove impurities or contaminants on the semiconductor wafer so as to ensure the material properties of subsequent processes.
Hundreds of thousands of PMOS transistors and NMOS transistors can be formed on the semiconductor wafer at the same time. In order to define which of the PMOS transistors and the NMOS transistors are to undergo an ion implantation process, a photoresist layer must be formed prior to the ion implantation process to cover a predetermined area of the semiconductor wafer. Each time an ion implantation process is completed, the photoresist layer must be removed and an RCA cleaning process must be performed to rinse the surface of the semiconductor wafer.
However, the RCA cleaning process uses specific proportions of H
2
O
2
, H
2
O, NH
4
OH, or HCl, which readily react with silicon or silicon oxide. Consequently, after the RCA cleaning process, a portion of the silicon substrate, or a silicon oxide layer on the semiconductor wafer, is etched. This disrupts the planarity of the semiconductor wafer. It also changes the thickness of the LDD on the silicon substrate, which effects the performance of the MOS transistor. Therefore, improving the method of forming the MOS transistor to prevent the damage caused by the RCA cleaning process becomes an important issue.
Please refer to FIG.
1
and FIG.
2
. FIG.
1
and
FIG. 2
are cross-sectional schematic diagrams of a method of forming a MOS transistor
20
according to the prior art. The MOS transistor
20
of the prior art is formed on a semiconductor wafer
10
that comprises a silicon substrate
12
, a gate oxide layer
14
positioned on the silicon substrate
12
, and at least one gate
16
positioned on a predetermined area of the silicon substrate
12
. First, a photoresist layer (not shown) is formed on the semiconductor wafer
10
to define an active region. Then, an ion implantation process is performed, using both the photoresist layer and the gate
16
as a mask, to form a doped layer
18
on the silicon substrate
12
around the gate
16
. The doped layer
18
is used as an LDD or an S/D of the MOS transistor
20
. Then, after the photoresist layer is removed, an RCA cleaning process is performed to remove impurities or contaminants on the semiconductor wafer
10
.
Since the cleaning solution used in the RCA cleaning process reacts with silicon, a portion of the silicon substrate
12
around the gate
16
is etched, forming an uneven surface after the RCA cleaning process, as shown in FIG.
2
. This decreases the size of the doped layer
18
and increases the series resistance from the drain to the source, which leads to slower operating speeds of the MOS transistor
20
.
In order to solve the above-mentioned problem, another prior art method of forming a MOS transistor uses a silicon oxide layer to protect the surface of the semiconductor wafer
10
so as to protect the silicon substrate
12
around the gate
16
from being etched. Please refer to FIG.
3
and FIG.
4
. FIG.
3
and
FIG. 4
are cross-sectional schematic diagrams of another method of forming a MOS transistor
24
according to the prior art. First, a silicon oxide layer
22
is formed on the semiconductor wafer
10
to cover the surface of the gate
16
and the gate oxide layer
14
. Then, a photoresist layer (not shown) is formed on the semiconductor wafer
10
to define an active region. An ion implantation process is the performed, using the photoresist layer and the gate
16
as a mask, to form a doped layer
18
on the silicon substrate
12
around the gate
16
. The doped layer
18
is used as an LDD or S/D of the MOS transistor
24
. Next, after the photoresist layer is removed, an RCA cleaning process is performed to remove impurities and contaminants on the semiconductor wafer
10
.
During the RCA cleaning process, a portion of the silicon oxide layer
22
is etched to form an uneven surface after the RCA cleaning process, as shown in FIG.
4
. The silicon oxide layer
22
remaining on the semiconductor wafer
10
protects the surface of the silicon substrate
12
around the gate
16
from being etched. This prevents the decrease in size of the doped layer
18
. However, during the ion implantation process, oxygen ions from the silicon oxide layer
22
diffuse into the doped layer
18
, resulting in oxide enhanced diffusion (OED). This changes the doping concentration of the doped layer
18
and effects the performance of the MOS transistor
24
. Furthermore, if boron ions are the primary dopants used in the ion implantation process, the boron ions in the doped layer
18
will diffuse into the silicon oxide layer
22
and thus decrease the concentration of boron ions in the doped layer
18
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a MOS transistor to prevent damage caused by RCA cleaning processes and ensure the performance of the MOS transistor.
In a preferred embodiment, the present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor. A portion of the first ion implantation layer that is not covered by the second ion implantation layer is used as a lightly doped drain (LDD). The protection layer is used to protect the surface of the silicon substrate from being etched during the RCA cleaning process so as to prevent an increase of electrical resistance in the LDD.
It is an advantage of the present invention that the protection layer made of silicon nitride is first formed on the semiconductor wafer to prevent the surface of the silicon substrate around the gate from being etched during the RCA cleaning process. Also, this protects the first ion implantation layer from oxygen ions during the first ion implantation process so as to prevent a decrease of the doping concentration of the first ion implantation layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5234850 (1993-08-01), Liao
patent: 6194279 (2001-02-01), Chen et al.
patent: 6200840 (2001-03-01), Chen et al.
patent: 6207520 (2001-03-01), Gardner et al.
Wolf et al., Silicon Processing for the VLSI Era vol. 1:

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