Method of forming a monolithic semiconductor integrated circuit

Details Method of forming a monolithic semiconductor integrated circuit Method of forming a monolithic semiconductor integrated circuit

1994-02-22

1997-04-08

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

257370, 257378, 438195, 438207, 438202, H01L 2170

Patent

active

056186886

ABSTRACT:
An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.

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