Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-17
2001-09-11
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000, C438S618000, C438S738000
Reexamination Certificate
active
06287914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and in particular, to a technology effectively applied to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
2. Description of the Related Art
The memory cell of a DRAM is arranged at each of the points of intersection of a plurality of word lines and a plurality of bit lines which are arranged in a matrix on the main surface of a semiconductor substrate, and is constituted by one MISFET (metal insulator semiconductor field effect transistor) for selecting a memory cell and one capacitance element (capacitor) for storing information connected in series thereto.
The above-mentioned MISFET for selecting a memory cell is constituted mainly by a gate oxide film, a gate electrode integrally formed with the word line, and a pair of semiconductor regions which constitute a source and a drain. The capacitance element for storing information is arranged on the top of the MISFET for selecting a memory cell and is electrically connected to one of the pair of source and drain. Also, the bit line is also arranged on the top of the MISFET for selecting a memory cell and is electrically connected to the other of the pair of source and drain.
The above-mentioned DRAM having the capacitance element for storing information on the top of the MISFET for selecting a memory cell, that is, having the so-called stacked capacitor structure adopts either a capacitor-over-bit line (COB) structure in which the capacitance element for storing information is arranged over a bit line or a capacitor-under-bit line (CUB) structure in which the capacitance element for storing information is arranged under the bit line, and the former structure (COB structure) is more suitable for making a finely patterned memory cell. This is because of the following reason; in order to increase the amount of stored charges of the finely patterned capacitance element for storing information, the capacitance element for storing information is required to have a three-dimensional structure to increase its surface area and in the case of the CUB structure in which the bit line is arranged over the capacitance element for storing information, the aspect ratio of a contact hole for connecting the bit line to the MISFET for selecting a memory cell is made extremely large and hence it is difficult to make the contact hole.
SUMMARY OF THE INVENTION
In a DRAM having the COB structure in which the capacitance element for storing information is arranged on the bit line, the bit line is arranged on the MISFET for selecting a memory cell via a silicon oxide film (a first silicon oxide film) and the capacitance element for storing information is arranged on the bit line via a silicon oxide film (a second silicon oxide film). And one of the pair of source and drain of the MISFET for selecting a memory cell is connected to the bit line through a contact hole formed in the first silicon oxide film and the other of the pair of source and drain of the MISFET for selecting a memory cell is connected to the capacitance element for storing information through a through hole formed in the second silicon oxide film between the gap neighboring bit lines and through a contact hole formed in the first silicon oxide film underlying the through hole formed in the second silicon oxide film.
Accordingly, if the pitch of the bit line is reduced in a DRAM having the COB structure to reduce the size of a memory cell, it is difficult to ensure an alignment allowance between the bit line and the through hole passing the gap between the bit lines, which in turn present a problem that a plug buried in the through hole and the bit line make a short circuit.
As a countermeasure to avoid the drawback described above, it is thought to adopt the so-called self-alignment contact (SAC) technology that the top and the side wall of the bit line is covered with a silicon nitride film and that a through hole is made in a self-alignment manner with respect to the bit line by using a difference in an etching rate between the silicon nitride film and the second silicon oxide film of the region where the through hole is made.
However, in the case where the self-alignment contact (SAC) technology is adopted in which the surrounding of the bit line is covered with the silicon nitride film, the dielectric constant of silicon nitride is more than two times that of silicon oxide and hence increases the parasitic capacitance of the bit line, which in turn presents another problem that it is difficult to detect a signal stored in the capacitance element for storing information.
As a second countermeasure to ensure an alignment allowance between the bit line and the through hole, it is thought to adopt a method in which the width of a photoresist film used for patterning a metal film for the bit line is made fine to make the width of the bit line fine. In order to make the width of the photoresist film fine, the photoresist film applied to top of the metal film for the bit line is exposed to light and developed to form the photoresist film having a width determined by the minimum size of the limit of resolution of a photolithography and then the photoresist film is anisotropically etched to further narrow the width thereof.
However, the above-mentioned method of making the width of the photoresist film fine by etching it in an anisotropic manner has some difficulty in controlling the amount of etching of the photoresist film with high accuracy and hence presents a problem that the stability in sized of the photoresist film is reduced after it is etched. Also, in the case where the metal film is patterned by using the photoresist film having a width finer than the minimum width determined by the limit of resolution of the photolithography, another problem is also presented that a variation in the amount of etching of the photoresist film increases and that the stability in size of the bit line is reduced.
Further, in the case where the photoresist film applied to the top of the metal film is finely patterned, still another problem is presented that a variation in the size of the photoresist caused by halation or the like comes apparent. Also, when a reflection preventing film or the like is formed on the film underlying the photoresist film as the countermeasure against the problem, a problem is presented that it reduces the controllability of etching.
Also, in the manufacturing process of the DRAM having the above-mentioned COB structure, in order to form the capacitance element for storing information on the top of the bit line with good yield, it is necessary to deposit a silicon oxide film (a second silicon oxide film) in the gap between the bit lines and on the top of the bit line and then to planarize the surface of the silicon oxide film using CMP method. For this reason, in order to ensure a polishing margin, it is necessary to leave the silicon oxide film to some extent of thickness on the top of the bit line, which results in increasing the level of the region where the memory cell is formed (memory array). As a result, this increases the aspect ratio of a connection hole for connecting an Al wiring formed on the top of the capacitance element for storing information to the MISFET of the peripheral circuit and hence reduces the manufacturing yield of the connection hole and reliability in connection of a conductive layer buried in the connection hole.
It is an object of the present invention to provide a technology for reducing the size of a memory cell of a DRAM by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography.
It is another object of the present invention to provide a technology for improving the detection sensitivity of a signal stored in a capacitance for storing information by reducing the capacitance parasitic on the bit line.
It is still another object of the present invention to provide a techno
Ogishima Atsushi
Shukuri Shoji
Uchiyama Hiroyuki
Antonelli Terry Stout & Kraus LLP
Fahmy Wael
Hitachi , Ltd.
Toledo Fernando
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