Method of forming a low voltage gate oxide layer and tunnel...

Details Method of forming a low voltage gate oxide layer and tunnel... Method of forming a low voltage gate oxide layer and tunnel...

2006-05-02

2006-05-02

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000, C438S257000, C438S258000

Reexamination Certificate

active

07037786

ABSTRACT:
A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps needed to form the devices.

REFERENCES:
patent: 5254489 (1993-10-01), Nakata
patent: 5736764 (1998-04-01), Chang
patent: 5882993 (1999-03-01), Gardner et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 6238979 (2001-05-01), Bergemont
patent: 6281089 (2001-08-01), Chen
patent: 6808989 (2004-10-01), Hurley et al.

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