Method of forming a local interconnect with improved etch...

Details Method of forming a local interconnect with improved etch... Method of forming a local interconnect with improved etch...

1999-10-14

2001-03-13

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C438S740000

Reexamination Certificate

active

06201303

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the formation of local interconnects in semiconductor processing technology, and more particularly, to the improvement of etch selectivity of an etch stop layer with respect to layers below and above the etch stop layer to prevent the disconnection of diffusion regions at field edges.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using local interconnects.
The local interconnect is typically a relatively low resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or a trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the density of the circuits increases there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
A problem arises in the formation of a local interconnect due to the relatively poor etch selectivity of the oxide dielectric material to the etch stop layer typically used to prevent overetching into a diffusion region. The overetching may lead to disconnection of the diffusion region at a field edge and result in a poor interconnection. This may best be understood by reference to
FIGS. 1-3
to illustrate the concern.
FIG. 1
depicts a cross-section of a semiconductor device arrangement during one step of a local interconnect formation process. A silicon substrate
10
has polycrystalline silicon (hereafter polysilicon) gates
12
and
14
formed thereon. The polysilicon gate
14
is actually formed on the field oxide
16
. A spacer
15
(such as an oxide spacer) provides a shielding of the substrate
10
directly under the spacer
15
during implantation or diffusion of dopant substrate
10
.
A plurality of silicide regions
18
are formed through conventional silicide techniques, for example, in a self-aligned silicide (“salicide”) technique. The material comprising the silicide regions
18
may be selected from different materials, such as titanium silicide, cobalt suicide, tungsten silicide, etc. Silicide regions
18
provide a low resistance contact for the semiconductor devices.
The doped active region
20
is provided in the substrate
10
as defined by the doping. Typically, a heating step is performed to activate the dopants following the introduction of the dopants into the substrate
10
.
An etch stop layer
22
is conformally deposited over the semiconductor wafer. An exemplary material for the etch stop layer is silicon oxynitride (SiON) and a conventional method of deposition is plasma enhanced chemical vapor deposition (PECVD). A layer of dielectric material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS), is deposited over the etch stop layer
22
and planarized. The dielectric layer
24
is then covered with a photoresist mask
26
which is patterned and developed with the desired local interconnect opening that is to be etched in the dielectric layer
24
. In this example of
FIG. 1
, the opening in the photoresist layer
26
is positioned to provide a local interconnect opening in the dielectric layer
24
that will eventually connect the gate
14
of one device with the active region
20
of another device.
An etching step is then performed that etches through the dielectric layer
24
in accordance with the pattern in the photoresist layer
26
. It is desirable to stop this first etching step at the etch stop layer
22
. However, as depicted in
FIG. 2
, it is often difficult to precisely stop the etch at the etch stop
25
layer
22
, especially at the edge of the field
16
. In this circumstance, the local interconnect opening
28
undesirably extends into the substrate
10
at area
30
. The unintended etching through the etch stop layer
22
allows the etchant to etch the silicide region
18
and the diffusion region
20
, creating the dip
30
into the substrate
10
.
As seen in
FIG. 3
, after the deposition of a liner (or “barrier layer”) that prevents diffusion of the conductive material into the other areas of the device, the local interconnect opening
28
is filled with a conductive material, such as tungsten
34
. However, there remains a disconnection of the diffusion region
20
at the edge of the field
16
, caused by the overetching through the etch-stop layer
22
during the etching of the dielectric layer
24
. This disconnection and the reduced contact of the conductive metal
34
to the silicide region
18
of the diffusion region
20
decreases the performance of the circuit, and in extreme circumstances, may cause circuit failure.
There is a need for an improved etch selectivity to prevent the weakness at the field edge and disconnection of the diffusion region during a local interconnect formation process.
SUMMARY OF THE INVENTION
This and other needs are met by the present invention which provides a method of forming a local interconnect comprising the steps of forming devices on a semiconductor wafer and forming silicide regions on the devices. A nitrogen containing etch stop layer is deposited over the devices and the suicide regions. Nitrogen is then implanted into the nitrogen-containing etch stop layer to introduce additional nitrogen into the etch stop layer. A dielectric layer is deposited on the etch stop layer and etched in accordance with a desired pattern with an etchant chemistry that is selective to the etch stop layer to form a local interconnect opening. This etch stop layer is then etched in accordance with the desired pattern with an etchant chemistry that is selective to the silicide regions. Conductive material is deposited in the local interconnect opening.
The implanting of nitrogen (e.g., by ion implantation) into the nitrogen-containing etch stop layer (such as conventional PECVD SiON) introduces additional nitrogen into the etch stop layer, making it “nitrogen-rich”. The additional nitrogen makes the etch stop layer slower to etch than conventionally deposited silicon oxynitride (PECVD SiON). Hence, the slowing down of the etch rate of the etch stop layer to an etchant chemistry used to etch the overlying dielectric layer increases the etch selectivity of the etch stop layer in comparison to untreated PECVD SiON. By improving the etch selectivity, the control of the etching process is increased so that the etching of the dielectric layer may be precisely stopped at the etch stop layer. This prevents the disconnection of the diffusion region at the field edge.
The earlier stated needs are met by another embodiment of the present invention which provides a local interconnect arrangement comprising a substrate layer and semiconductor devices that are on the substrate. Silicide regions are provided on the semiconductor devices. A nitrogen-rich etch stop layer is located on portions of some of the silicide regions, the etch stop layer including implanted nitrogen. A dielectric layer is on the etch stop layer. A local interconnect opening extends through

Affiliated with

Also associated with

Rating

Method of forming a local interconnect with improved etch... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a local interconnect with improved etch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a local interconnect with improved etch... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2502506