Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-17
2003-07-22
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S615000
Reexamination Certificate
active
06596621
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the joining of electronic devices to a substrate through a solder connection and, more particularly, relates to the joining of electronic devices such as chips, capacitors and the like to a suitable ceramic or organic substrate through a lead-free solder connection.
The so-called controlled collapse chip connection (also known as C
4
) is a means of connecting chips (also known as semiconductor devices), capacitors and the like to an organic or ceramic package (also known as an electronic substrate). The means of connecting chips having C
4
connections is actually an array of small solder balls on the surface of the chip, capacitor or the like (hereafter collectively referred to as an electronic device).
In C
4
structures, the electronic device wiring is terminated by a plurality of metal films (also referred as a metal stack) that form the ball-limiting metallurgy (BLM). The BLM is sometimes referred to as under bump metallurgy (UBM). The BLM defines the size of the solder bump after reflow, provides a surface that is wettable by the solder and that reacts with the solder to provide good adhesion and acceptable reliability under mechanical and heat stress, and is a barrier between the electronic device and the metals in the interconnection.
A typical BLM is a thin film stack consisting of a Cr or TiW adhesion layer, a phased-in CrCu layer and then Cu. The solder typically used is a Pb/Sn solder with high Pb-content of 95 weight percent or more. Sn is kept to a minimum, usually less than 5 weight percent because Sn reacts readily with the Cu to form usually undesirable intermetallics. The higher the Sn, the more the solder reacts with the Cu. Consequently, there may also be a Ni or Co barrier layer to either protect the Cu layer from being consumed by the solder or protect the layers of the BLM underneath the Cu layer.
Solder alloys containing Pb are now recognized as being harmful to the environment so there is considerable interest in going to Pb-free solders. Two commercially-available lead free solders are Sn—Ag and Sn—Ag—Cu.
Hur et al. U.S. Pat. No. 6,013,572, the disclosure of which is incorporated by reference herein, discloses a method to fabricate a Sn/3.5 weight percent Ag solder bump by plating of a first thick layer of Ag and a second layer of Sn upon a BLM consisting of a first layer of Ti, Cr or TiW and a second layer of Cu or Ni. The BLM layers may be formed by sputtering. After reflow, the SnAg alloy solder bump is formed.
Andricacos et al. U.S. Pat. No. 5,937,320, the disclosure of which is incorporated by reference herein, discloses a method of forming the BLM in which a Ni barrier layer is plated onto the BLM to protect the underlying Cu layer from attack by a PbSn solder. It is noted therein that interconnections with no remaining Cu will not survive the mechanical stresses of thermal cycling.
Cook et al. U.S. Pat. No. 5,719,070, the disclosure of which is incorporated by reference herein, discloses a BLM of Ti/Ni/Cu/Au which is joined with Pb/Sn solder or other suitable solder such as bismuth solders. Both the BLM and solder are formed by evaporation. The purpose of the Ni layer is to reduce corrosion of the underlying refractory metal The thickness of the Ni layer is in the range of 400 to 1000 Angstroms.
Schatzberg U.S. Pat. No. 4,756,467, the disclosure of which is incorporated by reference herein, discloses the sequential plating of Ag then Sn on a Cu wire followed by heating to form a Ag—Sn interface layer between the respective Sn and Ag layers.
Kurihara Published Patent Application 1-264233, the disclosure of which is incorporated by reference herein, discloses a reduced stress Cu/Cr/Ni—Cu/Au BLM onto which solder is placed.
Research Disclosure, Number 328 (August 1991), the disclosure of which is incorporated by reference herein, discloses a Cr/Au (or Ni)/Cu/Au (or Ni)/Cr capture pad.
Notwithstanding the efforts of those above, there remains a need for a BLM that is compatible with a lead-free solder.
Accordingly, it is a purpose of the present invention to have a BLM that is compatible with a lead-free solder.
It is another purpose of the present invention to have a BLM compatible with a lead-free solder that is readily manufacturable.
It is yet another purpose of the present invention to have a BLM compatible with a lead-free solder that is protected from dissolution in the lead-free solder.
These and other purposes of the present invention will become more apparent after referring to the following description of the invention in conjunction with the accompanying Figures.
BRIEF SUMMARY OF THE INVENTION
The purposes of the invention have been achieved by providing a method of forming a lead-free solder alloy on an electronic substrate, the method comprising the steps of:
(a) obtaining an electronic substrate having a pad;
(b) forming a metal stack on the pad comprising:
(i) depositing an adhesion layer on the pad;
(ii) depositing a nickel layer on the adhesion layer;
(iii) evaporating or plating a copper layer on the nickel layer; and
(iv) evaporating or plating quantities of tin and silver on the copper layer; and
(c) heating the electronic substrate and the metal stack to a predetermined temperature to cause melting of the tin and silver and at least a portion of the copper so as to form a lead-free tin, silver and copper alloy on the electronic substrate.
REFERENCES:
patent: 4756467 (1988-07-01), Schatzberg
patent: 5390080 (1995-02-01), Melton et al.
patent: 5719070 (1998-02-01), Cook et al.
patent: 5937320 (1999-08-01), Andricacos et al.
patent: 6013572 (2000-01-01), Hur et al.
patent: 6224690 (2001-05-01), Andricacos et al.
patent: 6310403 (2001-10-01), Zhang et al.
patent: 6413851 (2002-07-01), Chow et al.
patent: 1-264233 (1989-10-01), None
Research Disclosure, Aug. 1991, No. 328 entitled “Improved Capture Pad Metallurgy”(32847).
Copeland Bruce Anthony
Gorrell Rebecca Yung
Takacs Mark Anthony
Travis, Jr. Kenneth J.
Wang Jun
Blecker Ira D.
International Business Machines - Corporation
Smoot Stephen W.
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