Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-11-07
2006-11-07
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S663000, C257S077000
Reexamination Certificate
active
07132355
ABSTRACT:
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.
REFERENCES:
patent: 4758531 (1988-07-01), Beyer et al.
patent: 5250837 (1993-10-01), Sparks
patent: 5753555 (1998-05-01), Hada
patent: 5763305 (1998-06-01), Chao
patent: 6060746 (2000-05-01), Bertin et al.
patent: 6064081 (2000-05-01), Robinson et al.
patent: 6437375 (2002-08-01), Beaman
patent: 6448129 (2002-09-01), Cho et al.
patent: 6518609 (2003-02-01), Ramesh
patent: 6617226 (2003-09-01), Surguro et al.
patent: 6624032 (2003-09-01), Alavi et al.
patent: 6642539 (2003-11-01), Ramesh et al.
patent: 6703290 (2004-03-01), Boydston et al.
patent: 6713378 (2004-03-01), Drynan
patent: 6716687 (2004-04-01), Wang et al.
patent: 6716719 (2004-04-01), Clampitt et al.
patent: 6746923 (2004-06-01), Skotnicki et al.
patent: 6878592 (2005-04-01), Besser et al.
patent: 6885069 (2005-04-01), Ohguro
patent: 2001/0010962 (2001-08-01), Chen et al.
patent: 2001/0017392 (2001-08-01), Comfort et al.
patent: 2001/0025985 (2001-10-01), Noble
patent: 2002/0081861 (2002-06-01), Robinson et al.
patent: 2003/0027406 (2003-02-01), Malone
patent: 2003/0153155 (2003-08-01), Wang et al.
patent: 2003/0211712 (2003-11-01), Chen et al.
patent: 2004/0241460 (2004-12-01), Bodell et al.
U.S. Appl. No. 11/035,298, filed Jan. 12, 2005, Blomiley et al.
Bashir et al.,Characterization and modeling of sidewall defects in selective epitaxial growth of silicon, J. Vac. Sci. Technol. B 13(3), pp. 928-935 (May/Jun. 1995).
U.S. Appl. No. 10/932,151, filed Sep. 1, 2004, Ramaswamy et al.
U.S. Appl. No. 10/931,924, filed Sep. 1, 2004, Ramaswamy et al.
Basceri Cem
Blomiley Eric R.
Ramaswamy Nirmal
Sandhu Gurtej S.
LandOfFree
Method of forming a layer comprising epitaxial silicon and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a layer comprising epitaxial silicon and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a layer comprising epitaxial silicon and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3704663