Method of forming a junction region in a semiconductor device

Details Method of forming a junction region in a semiconductor device Method of forming a junction region in a semiconductor device

1999-12-22

2002-09-24

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000

Reexamination Certificate

active

06455366

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of forming a junction region in a semiconductor device. More particularly, the present invention relates to a method of forming a junction region in a semiconductor device by which, when applying an elevated source/drain junction using a selective epitaxial technology to the device as the integration degree of the semiconductor device increases, the elevated source/drain junction is applied only to the cell area; and source/drain ion implantation process and thermal process are performed with a nitride film being capped at the peripheral area, thus resulting in an improved characteristic of the device junction both at the source/drain regions and an improved characteristic of transistors in the semiconductor device.
2. Description of the Prior Art
Generally, as the integration degree of the semiconductor device increases, during a subsequent process of forming a contact, a known epitaxial technology is used to apply the elevated source/drain junction to the device so as to improve the contact resistance while securing a contact margin.
FIGS. 1
a
through
1
d
show sectional views of a device for illustrating a conventional method of forming a junction in a semiconductor device. The method of forming a junction shown by reference to
FIGS. 1
a
through
1
c
can be applied to both the cell region and peripheral circuit regions, and
FIG. 1
d
shows an enlarged view of the junction formed at the peripheral circuit region.
Referring now to
FIG. 1
a
, a device separation film
12
is formed on a semiconductor substrate
11
to define an active region. Then, after a gate oxide film
13
, a conductive layer for gate electrode
14
and a mask insulation film
15
are sequentially formed, a gate electrode
14
is formed on the semiconductor substrate
11
in the active region through etching process using a gate mask.
Next, as shown in
FIG. 1
b
, after a gate spacer
16
is formed at the side wall of a pattern in which the gate oxide film
13
, the gate electrode
14
and the mask insulation film
15
are stacked, an undoped epitaxial silicon layer
17
is selectively formed on it using chemical vapor deposition (CVD) method.
Thereafter, referring to
FIG. 1
c
, after source/drain ion implantation process is performed, a thermal process for activating ion-implanted dopant is performed to make the dopants a little diffuse into the semiconductor substrate
11
, thus forming a elevated source/drain junction
18
.
However, the method of forming an elevated source/drain junction using a conventional selective epitaxial technology is to grow an undoped silicon layer using epitaxial technology and then to control the energy of ion implanted and the amount of implanted ions to form a junction. Then, as the source/drain junction in the peripheral area requires relatively a higher rate of source/drain concentration compared to that of the cell area, severe requirements for ion implantation conditions has to be set. Under these conditions, upon ion implantation, it makes the apparatus vulnerable to metal contamination. As well known in the art, also due to facet inevitably occurring upon a selective epitaxial formation, it degenerates the phenomenon by which the undoped silicon layer is deeply formed toward the portion in which the channel is formed, as shown in
FIG. 1
d
. Thus, it is well known that it is a factor which generally degrades the transistor characteristic in the peripheral circuit area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a junction in a semiconductor device by which, when applying an elevated source/drain junction using a selective epitaxial technology to the device as the integration degree of the semiconductor device increases, the elevated source/drain junction is applied only to the cell area and source/drain ion implantation process and thermal process are performed with a nitride film being capped at the peripheral circuit area, thereby making metal contamination low and thus lowering diffusion of dopants that is suppressed under a high compressive stress so that the junction depth can be reduced and the characteristic of the device junction at both areas can be improved.
In order to accomplish the above object, the method of forming a junction region in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming gate electrodes at a cell area and a peripheral circuit area, respectively, which are defined in a semiconductor substrate; forming gate spacers at side walls of each of the gate electrodes and forming a nitride film only at said peripheral circuit area; selectively forming a doped epitaxial silicon layer on said semiconductor substrate in the cell area; performing source/drain implantation process to the peripheral circuit area covered with the nitride film and then performing thermal process for activating ion implanted dopants to forming a source/drain junction only at the peripheral circuit area, so that, during the thermal processing process, the dopants within said doped epitaxial silicon layer are diffused to form an elevated source/drain junction at the cell area; and removing any nitride film remaining at said peripheral circuit area to form an interlayer insulation film.


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