Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-06
2002-11-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S221000, C438S321000, C438S697000, C438S704000
Reexamination Certificate
active
06482697
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor memory device, and more particularly to a method of forming a non-volatile semiconductor memory device having a high density integration of size-reduced memory cells having floating gate MOS field effect transistors with an accurately controlled gate length.
FIG. 1
is a fragmentary circuit diagram illustrative of a partial array structure of memory cells having floating gate MOS field effect transistors in the conventional non-volatile semiconductor memory device. Each of the memory cells CELL comprises a pair of a storage capacitor and a floating gate MOS field effect transistor. The memory cell array has a plurality of bit lines BL extending in a first direction. The memory cell array also has a plurality of word lines WL extending in a second direction perpendicular to the first direction. The memory cell array comprises a plurality of memory cell columns, each of which extends along the first direction and between adjacent two of the bit lines BL. Since each of the memory cells has the single pair of the floating gate MOS field effect transistor and the storage capacitor, each of the memory cell columns has a plurality of the floating gate MOS field effect transistors. Each of the floating gate MOS field effect transistors has a source, a drain, a floating gate and a control gate. Sources of the floating gate MOS field effect transistors in the each memory cell column are commonly connected to each other through a common source line. Drains of the floating gate MOS field effect transistors in the each memory cell column are also commonly connected to each other through a common drain line. This common drain line is further connected through a drain selecting transistor SWD to the corresponding bit line BL. The drain selecting transistor SWD has a gate connected to a drain selector line DSEL, so that the common drain line is made connected to the bit line BL in accordance with a drain selecting signal transmitted on the drain selector line DSEL connected to the gate of the drain selecting transistor SWD. A source line SL is further provided which extends in the second direction. The above common source line is connected through a source selecting transistor SWS to the source line SL. The source selecting transistor SWS has a gate connected to a source selector line SSEL, so that the common source line is made connected to the source line SL in accordance with a source selecting signal transmitted on the source selector line SSEL connected to the gate of the source selecting transistor SWS. Each of the memory cell rows comprises the plural floating gate MOS field effect transistors having control gate electrodes connected to the corresponding word line WL. The above circuit configuration forms an AND-type memory. In accordance with the AND-type memory, it is necessary that the sources and drains of the floating gate MOS field effect transistors on the memory cell column TCELLm are separated from the sources and drains of the floating gate MOS field effect transistors on the adjacent memory cell column TCELLn. It is necessary that the control gate electrodes serving as the word line extend in the gate length direction. By contrast to the AND-type memory, a NOR-type memory has a different structure that the source regions of the floating gate MOS field effect transistors on the each memory cell column are common to each other, whilst the drain regions thereof serve as the bit line. A contact is provided for every one or plural memory cells. For these reasons, the control gates of the floating gate MOS field effect transistors extend in the gate width direction. Since as described above, the AND-type memory has the structure that the control gate electrodes serving as the word line extend in the gate length direction, it is impossible that after the control gate and the floating gate have been formed, then the source and drain region are formed. It is necessary for the AND-type memory that the floating gate is firstly formed and then the source and drain regions are secondly formed before the control gate is finally formed.
FIGS. 2A through 2E
are fragmentary cross sectional elevation views illustrative of the first conventional method of forming the floating gate MOS field effect transistor included in the AND-type memory. This first conventional method is the applicant's admitted prior art.
With reference to
FIG. 2A
, shallow trench isolations
202
are selectively formed in an upper region of a p-type silicon substrate
201
thereby to define a memory cell formation region
220
in the upper region of a p-type silicon substrate
201
, wherein the memory cell formation region
220
is surrounded by the trench isolations
202
. A tunnel gate insulation film
205
is formed on the memory cell formation region
220
. A first polycrystalline silicon film
206
is formed on the tunnel gate insulation film
205
. A first silicon oxide film
221
is formed on the first polycrystalline silicon film
206
. A first silicon nitride film
222
is formed on the first silicon oxide film
221
. An antireflective film
223
is formed on the first silicon nitride film
222
to form multilayer laminations. A resist pattern
224
is formed on the antireflective film
223
. An anisotropic etching process is carried out by use of the resist pattern
224
as a mask to pattern the multilayer laminations thereby forming a gate structure
225
, which comprises the tunnel gate insulation film
205
, the first polycrystalline silicon film
206
, the first silicon oxide film
221
, the first silicon nitride film
222
and the antireflective film
223
. The used resist pattern
224
is removed.
With reference to
FIG. 2B
, a first ion-implantation process is carried out by use of the gate structure
225
as a mask for introducing an n-type impurity into selected upper regions of the memory cell formation region
220
except under the gate structure
225
thereby to selectively form n
−
-type lightly doped diffusion regions
204
in the selected upper regions of the memory cell formation region
220
except under the gate structure
225
, wherein the n
−
-type lightly doped diffusion regions
204
are defined by the shallow trench isolation regions
202
and are self-aligned to the gate structure
225
. An oxide film is entirely formed which extends over the shallow trench isolation regions
202
, the n
−
-type lightly doped diffusion regions
204
and side walls and a top surface of the gate structure
225
. An anisotropic etching process is then carried out to the oxide film so as to selectively leave the oxide film on the side walls of the gate structure
225
, whereby side wall oxide films
209
are formed on the side walls of the gate structure
225
. A second ion-implantation process is carried out by use of the gate structure
225
and the side wall oxide films
209
as a mask for introducing an n-type impurity into selected upper regions of the memory cell formation region
220
except under the gate structure
225
and the side wall oxide films
209
thereby to selectively form n
+
-type source and drain regions
203
S and
203
D in the selected upper regions of the memory cell formation region
220
except under the gate structure
225
and the side wall oxide films
209
, wherein the n
+
-type source and drain regions
203
S and
203
D are defined by the shallow trench isolation regions
202
and are self-aligned to the side wall oxide films
209
. As a result, the n -type lightly doped diffusion regions
204
remain under the side wall oxide films
209
. The boundaries between the n
+
-type source and drain regions
203
S and
203
D and the n
−
-type lightly doped diffusion regions
204
are aligned to the outside edges of the side wall oxide films
209
.
With reference to
FIG. 2C
, a first inter-layer insulator
210
is entirely formed over the shallow trench isolation regions
202
, the n
+
-type source and drain regions
203
S and
203
D, the
Rocchegiani Renzo N.
Smith Matthew
Young & Thompson
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