Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-10
2001-10-02
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S529000
Reexamination Certificate
active
06297108
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a doped region on a semiconductor wafer, and more particularly, to a method of forming a doped region with a double diffuse drain (DDD) on a semiconductor wafer.
2. Description of the Prior Art
A double diffuse drain (DDD) is used as a source/drain in a high voltage metal-oxide semiconductor (HVMOS) transistor. It provides a high breakdown voltage for the HVMOS transistor to prevent electrostatic discharge that may result in the destruction of a semiconductor device. It also provides a solution to hot electron effects, which are due to shorted channel lengths in a MOS transistor, and so prevents electrical breakdown in the source/drain under high voltage loading.
However, in a typical semiconductor manufacturing process, a semiconductor wafer not only comprises HVMOS transistors, but also comprises many low voltage metal-oxide semiconductor (LVMOS) transistors. How to integrate the HVMOS transistor process with the LVMOS transistor process, and how to create large amounts of both HVMOS and LVMOS transistors simultaneously on a semiconductor wafer is an important issue at the present time.
Please refer to FIG.
1
and FIG.
2
. FIG.
1
and
FIG. 2
are cross-sectional diagrams of a method of forming a DDD on an N-type HVMOS transistor according to the prior art. The prior art N-type HVMOS transistor
10
is formed on a predetermined area of a semiconductor wafer
12
. The semiconductor wafer
12
comprises a p-type silicon substrate
14
, a gate oxide layer
16
positioned on the p-type silicon substrate
14
, a poly gate
18
positioned on the gate oxide layer
16
, two spacers
20
around the poly gate
18
, and two field oxide (FOX) layers
22
positioned adjacent to the two sides of the HVMOS transistor
10
. The field oxide layers
22
provides good insulation between the HVMOS transistor
10
and other devices.
As shown in
FIG. 1
, in the prior art method of forming a source/drain of the DDD in the N-type HVMOS transistor
10
, a lithographic process is performed to coat a photoresist layer
24
on the semiconductor wafer
12
. Then an exposure process and a development process are performed to form openings
26
in the photoresist layer
24
. The openings
26
are used to define a position of the source/drain, and the photoresist layer
24
is used as a mask in a subsequent ion implantation process.
A first ion implantation process is performed with an energy of 50 to 180 KeV to implant 10
14
to 10
15
ions/cm
2
of phosphorus (p
31
) ions into a portion of the P-type silicon substrate
14
not covered by the photoresist layer
24
, forming a first doped region
28
. Then, a second ion implantation process is performed with an energy of 50 to 150 KeV to implant 10
15
to 5×10
15
ions/cm
2
of arsenic (As) ions into the same area of the first doped region
28
so as to form a second doped region
30
. As show in
FIG. 2
, a resist stripping process is performed to remove the photoresist layer
24
on the semiconductor wafer
12
. A thermal annealing process is performed to drive the phosphorus ions in the first doped region
28
into the silicon substrate
14
so as to form a lightly N doped region
32
, and to simultaneously drive the arsenic ions in the second doped region
30
into the silicon substrate
14
so as to form a heavily N
+
doped region
34
. The doped regions
32
and
34
overlap each other, and a doped region
36
with a double diffuse drain (DDD) is thus formed. The doped region
36
is used as the source/drain in the HVMOS transistor
10
. The silicon lattice in the silicon substrate
14
, which may have been destroyed by the ion implantation processes, can be restored during a thermal annealing process.
If two doped regions with a DDD in a P-type HVMOS transistor need to be formed, the above steps can still be used, changing only some of the materials or implantation energies. For example, the P-type silicon substrate
14
is first replaced by an N-type silicon substrate. The phosphorus ions in the first implantation process are replaced by boron (B) ions with a new implantation energy of 30 to 70 KeV. The arsenic ions in the second ion implantation process are replaced by BF
2
+
ions with a new implantation energy of 50 to 120 KeV. Hence, the source/drain of the DDD in a P-type HVMOS transistor can be formed with the same equipment that is used to form an N-type HVMOS transistor.
However, when HVMOS transistors are formed on the semiconductor wafer, the semiconductor wafer also comprises many LVMOS transistors. The structures of HVMOS transistors and of LVMOS transistors are different, and so the thermal budgets of the processes needed for the formation of the HVMOS transistors and the LVMOS transistors are different, too. The source of the HVMOS transistor usually needs to withstand high breakdown voltages, so the DDD in an HVMOS transistor is formed using a thermal process that has a high temperature and a long treatment period time. However, such a thermal treatment will drive the ions in the doped regions of the LVMOS transistors into the silicon substrate beyond a predetermined depth, resulting in unstable characteristics of the LVMOS transistors. Consequently, it is difficult to integrate the manufacturing processes of HVMOS transistors with those of LVMOS transistors under conditions that maintain the original characteristics of the devices.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a source/drain of a DDD in an HVMOS transistor to solve the above problems.
In a preferred embodiment, the present invention provides a method of forming a doped region on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon oxide layer positioned on the silicon substrate, and a silicon nitride layer positioned on a predetermined area of the silicon oxide layer. A lithographic process is performed to form a photoresist layer of even thickness on the semiconductor wafer. The photoresist layer is used as a mask and comprises at least one opening over the silicon nitride layer. A first ion implantation process is performed to implant a specific dosage of dopants into the silicon substrate under the opening. The photoresist layer on the semiconductor wafer is removed completely. A thermal oxidation process is then performed to form a field oxide layer in the region not covered by the silicon nitride layer, and to simultaneously drive the dopants into the silicon substrate so as to form a doped region. The silicon nitride layer on the semiconductor wafer is then removed completely. A poly gate on the substrate in the area between the two doped regions is formed and a spacer around the sides of the poly gate is formed. Then a second ion implantation process is performed to implant a specific dosage of dopants into a predetermined region of the two doped regions so as to form two doped regions each with a double diffuse drain (DDD).
It is an advantage of the present invention that HVMOS transistors and LVMOS transistors can be simultaneously formed on a semiconductor without affecting their original characteristics.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5300797 (1994-04-01), Bryant et al.
patent: 5376568 (1994-12-01), Yang
patent: 5786252 (1998-07-01), Ludikhuize et al.
patent: 5910666 (1999-06-01), Wen
Chaudhuri Olik
Eaton Kurt
Hsu Winston
United Microelectronics Corp.
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