Method of forming a high voltage device

Details Method of forming a high voltage device Method of forming a high voltage device

2009-02-23

2011-11-08

Dang, Phuc (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S289000, C438S302000, C257S339000, C257SE21427

Reexamination Certificate

active

08053319

ABSTRACT:
A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

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Leonard Rubin et al., Narrow n+/p+ isolation in retrograde well implants, Solid State Technology Magazine, Jul. 1, 2003, pp. 119-125, vol. 46 Issue 7, Solid State Technology, USA.

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