Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth from gaseous state combined with subsequent...
Reexamination Certificate
2002-02-21
2004-04-20
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth from gaseous state combined with subsequent...
C438S508000, C438S763000
Reexamination Certificate
active
06723622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a low dislocation defect germanium layer and in particular, to semiconductor devices comprising a low dislocation defect germanium layer grown on an ultra-thin silicon-germanium buffer layer. The present invention further concerns the methods for making and using such devices.
2. Discussion of Related Art
Forming high quality germanium layers on a substrate is desirable. Germanium (Ge) layers grown on a silicon (Si) substrate can be used to make high mobility devices. There is thus increasing interest in using SiGe alloy as a material for microelectronic and optoelectronic device applications. Ge is known to have high carrier mobility (e.g., high hole and electron mobility) and optical absorption as compared to Si. This is one reason why Ge is useful for devices that require enhanced performance and/or high quantum efficiency. Examples of devices that would benefit from the use of a Ge film include metal-oxide-semiconductor (MOS) transistors, optical detectors, and other optoelectronic devices, to name a few.
There is a large lattice-mismatched of about 4% between the Ge and the Si. The mismatched lattice hinders the growth of coherently strained Ge beyond a critical thickness, at which point there is formation of misfit dislocations. These mistfit dislocations subsequently form threading segments, threading dislocations that penetrate the entire epitaxial layer and terminate at the free surface. Threading dislocations are undesirable defects since they cause highly faulted epitaxial Ge layers which reduces the carrier mobility, adversely affects the electronic quality and performance reliability of various electronic devices. Threading dislocations also increase the dark current in an optical detector, which induces noises in the signal. And, threading dislocations increase current leakage between the source and drain regions of a MOS transistor.
With lattice mismatch making growing Ge directly on Si a problem, SiGe buffer layers have been used to minimize the effect of this problem. The SiGe buffer layers are often graded, from 0% Ge to 100% Ge, at a low rate of change, typically 10-20% Ge/&mgr;m. To deposit the Ge layer, SiGe is first deposited as a buffer layer on a substrate (e.g., Si wafer), and Ge is finally deposited on the SiGe. This very low-slope grading scheme enables the gradual increase of the lattice constant of the semiconductor, which minimizes the generation of misfit and threading dislocation. However, the gradual change from 0% Ge to 100% Ge is often slow, and as such, necessitates the use of very thick buffer layers, typically 1-5 &mgr;m.
The presence of thick buffer layers poses several problems. Typical deposition times for the buffer layer can be in excess of four hours, which imposes a severe penalty on factory throughput in high volume applications and increases wafer fabrication costs, particularly when single-wafer epitaxial reactors are used. High performance Si CMOS fabrication techniques are moving away from the use of bulk Si. The most promising device structures which will allow the extension of Si CMOS technology below 30 nm are believed to be depleted substrate (DST) and double-gate (DG) devices. Both DST and DG applications require active layers thinner than 500 A (0.005 &mgr;m). The presence of thick buffer layers required by current state-of-the-art Ge deposition techniques makes Ge incompatible with these high-performance structures. There is also significant interest in using Ge detectors for optical clock applications in conventional CMOS technology. The use of thick buffer layers will result in severe planarity issues between the portion of the chip containing the Ge detector and the parts of the die containing Si-only devices. Films deposited in this manner develop significant surface undulations, which tend to trap dislocations. The trapping of dislocations causes new dislocations to be generated in order to relieve the stress developed due to lattice mismatch, which increases the overall dislocation density in the deposited layer. An intermediate chemical mechanical polishing (CMP) step may be necessary to restore planarity of the surface and relieve dislocation pileup.
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Boyanov Boyan
Murthy Anand
Soman Ravindra
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Jr. Carl Whitehead
Smoot Stephen W.
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