Method of forming a gate structure

Details Method of forming a gate structure Method of forming a gate structure

2003-07-14

2004-06-22

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000

Reexamination Certificate

active

06753225

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a gate structure, and more particularly, to a method for preventing the word line and the bit line from generating short circuits.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is composed of many memory cells, and each memory cell has a metal oxide semiconductor (MOS) transistor and a capacitor. The gate of the MOS transistor (also known as word line) serves as a switch of the transistor, while the drain or the source is connected to a bit line for writing and erasing data.
Refer to FIG.
1
and
FIG. 2
, which are schematic diagrams illustrating a method of forming a controlling gate of a DRAM according to the prior art. As shown in
FIG. 1
, first a substrate
10
having at least a stacked gate
12
is provided. The stacked gate
12
has a gate insulating layer
14
, a polysilicon layer
16
, a silicate layer
18
, and a cap layer
20
.
As shown in
FIG. 2
, a chemical vapor deposition (CVD) process is performed to form a silicon nitride layer on the substrate
10
. Then an anisotropic process is performed to form a spacer
22
on the walls of the stacked gate
12
.
After that, an implantation process is performed to form a drain (not shown) and a source (not shown) in the substrate
10
.
After forming the stacked gate
12
, the prior art method further comprises the steps of forming a bit line. Refer to
FIG. 3
to
FIG. 5
which are schematic diagrams illustrating a method of forming the bit line. As shown in
FIG. 3
, a barrier layer
24
is deposited on the substrate
10
and on the stacked gate
12
after forming the stacked gate
12
. Then a borophosphosilicate glass (BPSG) layer
26
is deposited on the barrier layer
24
, and a flow process is performed to planarize the BPSG layer
26
. Finally, a chemical mechanical polishing (CMP) process is performed to remove the BPSG layer
26
over the top surface of the cap layer
20
. The function of the barrier layer
24
is to prevent the ions of the BPSG layer
26
from diffusing to the substrate
10
during the flow process.
As shown in
FIG. 4
, a dielectric layer
28
(such as a TEOS layer) is deposited on the stacked gate
12
. Then a photo-etching process is performed to remove parts of the dielectric layer
28
, the BOSG layer
26
, and the barrier layer
24
for forming a contact hole
30
.
Finally as shown in
FIG. 5
, a bit line
32
is formed and electrically connected to the drain (not shown) or the source (not shown).
The prior art method utilizes the spacer to prevent the word line and the bit line from generating short circuits. As the integration of semiconductor elements increases and the dimension decreases day by day, however, the spacer is easily destroyed when forming the contact hole due to misalignment. The bit line and the silicate layer are easily short circuited under this condition, especially when the dimension of the semiconductor process is lower than 0.11 micrometers.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method of forming a controlling gate of a DRAM for solving the above-mentioned problems.
According to the claimed invention, a method of forming a controlling gate of a DRAM is disclosed. The method comprises: providing a substrate having at least a stacked gate, the stacked gate comprising a gate insulating layer, a polysilicon layer, a silicate layer, and a cap layer; depositing a sacrificial layer on the stacked gate; etching back the sacrificial layer to expose the cap layer and an upper portion of the silicate layer; removing a portion of the exposed silicate layer to form a recess; removing the sacrificial layer; filling a silicon nitride layer in the recess; and forming a spacer on walls of the stacked gate.
It is an advantage of the claimed invention that a recess is formed in the upper portion of the silicate layer, and a silicon nitride layer is filled intothe recess. Therefore the short circuit problem is effectively avoided.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 6365497 (2002-04-01), Gonzalez

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