Method of forming a gate spacer on a semiconductor wafer

Details Method of forming a gate spacer on a semiconductor wafer Method of forming a gate spacer on a semiconductor wafer

1999-04-19

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438439, 438366, 438303, 438230, 438184, H01L 213205, H01L 214763

Patent

active

061331317

ABSTRACT:
The present invention relates to a method of forming a gate spacer on the semiconductor wafer. Two dielectric layers are first formed on the surface of the semiconductor wafer, the first dielectric layer is an USG dielectric layer and the second dielectric layer is a SOG dielectric layer. The SOG dielectric layer is formed by a spincoating process to create a flat surface on the semiconductor wafer. Afterward, the plasma etching, wet etching and dry etching processes are sequentially performed to remove the SOG dielectric layer and USG dielectric layer. Finally, the spacer is formed on the side-wall of the gate.

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patent: 5045486 (1991-09-01), Chittipeddi et al.
patent: 5702568 (1997-12-01), Shin et al.
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patent: 5747381 (1998-05-01), Wu
patent: 5914498 (1999-06-01), Suzawa et al.
patent: 5976939 (1999-11-01), Thompson et al.

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