Method of forming a gate in a stack gate flash EEPROM cell

Details Method of forming a gate in a stack gate flash EEPROM cell Method of forming a gate in a stack gate flash EEPROM cell

2000-06-28

2001-03-20

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06204125

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell and more particularly, to a method of forming a gate in a stack gate flash EEPROM cell capable of improving an erase operation speed by reducing a lateral bird's beak of an ONO dielectric layer and increasing a coupling ratio, wherein the lateral bird's beak occurs during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate.
2. Description of the Prior Art
Hereinafter, a method of forming a gate in a conventional stack gate flash EEPROM cell will be described with reference to FIG.
1
.
In
FIG. 1A
, there is shown a method of forming a gate in a stack gate flash EEPROM cell. Referring to
FIG. 1A
, a stack gate having a stack structure of a floating gate
3
and a control gate
5
is formed on a semiconductor substrate
1
. A tunnel oxide layer
2
is formed between the floating gate
3
and the semiconductor substrate
1
. A dielectric layer
4
is formed between the floating gate
3
and the control gate
5
. An ONO structure is generally applicable to the dielectric layer
4
.
In
FIG. 1B
there is shown a cross-sectional view of the dielectric layer
4
of ONO structure. Referring to
FIG. 1B
, the dielectric layer
4
is formed with a lower oxide layer
4
a
, a nitride layer
4
b
and an upper oxide layer
4
c
. In the conventional method of forming a cell gate, however, in order to reduce a damage after forming a cell gate, a reoxidation process is carried out at a temperature of 850° C. At this point, polysilicons adjacent to the ONO structure of the dielectric layer
4
are oxidized, and, as shown in
FIG. 1B
, the thickness of the lower and upper oxide layers
4
a
and
4
c
of the ONO dielectric layer
4
becomes thick. Consequently, the lateral bird's beak
4
d
occurs.
It is supposed that the causes of the lateral bird's beak is due to an etching damage occurring adjacent to the ONO dielectric layer
4
during an etching process for forming a cell gate as well as an oxidation of the polysilicon in a boundary region between oxide layers
4
a
and
4
c
constituting the ONO dielectric layer
4
and gates
3
and
5
formed of the polysilicon during the reoxidation process. Since a capacitance is inversely proportional to a thickness of an insulating material, as the thickness of the ONO dielectric layer
4
is increasing, a value of the capacitance is decreased, thereby reducing a coupling ratio. In the cell operation, the coupling ratio is a very important factor.
For example, if a voltage of 10 V is applied to the control gate, when the coupling ratio is 0.5, the voltage applied to the floating gate becomes 5 V. Hence as the coupling ratio becomes increasing, the voltage applied to the floating gate is increased. This plays an important role in a cell erase operation. The cell erase generally employs the F-N tunneling. Since the voltage applied to the floating gate is increased as the coupling ratio becomes larger, it is advantageous to F-N tunnel the electrons on the floating gate to a channel region or source region. Since the coupling ratio is decreased due to an increase of the thickness in the ONO dielectric layer caused by the lateral bird's beak, the cell erase operation speed is lowered. Consequently, it causes a deterioration of the entire cell erase operation speed. A desirable cell erase operation speed can be obtained when the coupling ratio of cell is above 0.6.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of forming a gate in a stack gate flash EEPROM cell capable of solving the above problems by increasing a coupling ratio through a reduction of a lateral bird's beak of an ONO dielectric layer.
In order to achieve the object of the present invention, a method of forming a gate in a stack gate flash EEPROM cell comprises the steps of forming a cell gate having a stack structure, wherein the stack structure has a tunnel oxide layer, a floating gate, a dielectric layer and a control gate stacked on a semiconductor substrate; forming an oxide layer as a first barrier layer on an entire upper portion including said cell gate; forming a nitride layer as a second barrier layer on an upper portion of said first barrier layer; carrying out a reoxidation process; and removing said nitride layer.


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