Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-09
2004-01-06
Le, D (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S304000, C438S305000
Reexamination Certificate
active
06673686
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of integrated circuits (IC's), and more particularly to the fabrication of memory IC's.
BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and a common type of semiconductor memory is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells arranged in an array, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
One type of DRAM storage capacitor is formed by etching deep trenches in a semiconductor substrate, and depositing a plurality of layers of conductive and insulating materials thereon in order to produce a storage capacitor that is adapted to store data, represented by a one or zero. Planar DRAM designs typically comprise an access FET disposed in a subsequently deposited layer, disposed above and to the side of the storage capacitor.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. More recent DRAM designs involve disposing the access FET directly above the storage capacitor, sometimes referred to as a vertical DRAM, which saves space and results in the ability to place more DRAM cells on a single chip.
A prior art vertical DRAM device
10
is shown in
FIG. 1
, after the formation of the memory cells
18
within deep trenches
16
. To form the memory cells
18
, a plurality of trenches
16
are formed in a semiconductor substrate
12
or workpiece having a pad nitride
14
, comprising silicon nitride, for example, disposed thereon. A storage capacitor
18
is formed within the bottom portion of the deep trenches
16
. The storage capacitor
18
includes a collar oxide
20
, buried strap
24
and capacitor inner plate
22
, for example. A buried plate may be disposed in the lower part of the trench (not shown). A trench top oxide (TTO)
26
is formed over the top surface of the storage capacitor
18
, and a gate electrode
28
is formed over the TTO
26
. A gate electrode contact
32
is disposed over the gate electrode
28
. The gate electrode contact
32
will be coupled in a subsequent processing step to an overlying conductive layer such as a wordline or bitline (not shown), in order to access the memory cell
18
, referred to as a CB etch, or contact to bitline etch.
To prevent shorts of the memory cell to the wordlines and bitlines, or from wordline to bitlines, typically the gate electrode contact
32
has a smaller width or diameter than the width or diameter of the gate electrode
28
. More particularly, the top of the deep trench
16
has a larger width than the gate electrode contact
32
width. At the point in the manufacturing process shown in
FIG. 1
, a temporary spacer
30
has been formed above the gate electrode
28
, between the gate contact
32
and the adjacent substrate
12
and pad nitride
14
. The temporary spacer
30
functions to reserve the space where a divot fill
62
will later be formed (see FIG.
3
). A thin oxide layer
34
has been formed on the edge of the pad nitride
14
adjacent the temporary spacer
30
, resulting from oxidation that has occurred during the various processing steps of the memory cell
18
, such as the formation of a gate oxide, for example.
The next step in the manufacturing process of the vertical DRAM device
10
typically comprises removing the pad nitride
14
, as shown in the prior art drawing of FIG.
2
. Because the temporary spacer
30
comprises silicon nitride, the same material as the pad nitride
14
, the temporary spacer
30
is removed during the removal of the pad nitride
14
. The nitride material
14
/
30
removal step results in a residual amount of oxide
34
remaining over the substrate
12
at the edge of the deep trenches
16
. A recess
35
or divot is created over the gate electrode
28
when the temporary spacer
30
is removed. The next step in the manufacturing process is to replace the temporary spacer
30
with a divot fill
62
, as shown in FIG.
3
. The divot fill
62
protects the gate electrode
28
during a subsequent gate electrode (GC) etch. The divot fill
62
also protects the gate electrode
28
during a subsequent CB etch.
SUMMARY OF THE INVENTION
Embodiments of the present invention achieve technical advantages as a gate electrode contact permanent spacer and method of forming thereof. The spacer is formed by removing temporary spacer material, depositing a first material over the top and sides of the gate electrode contact and exposed portions of the workpiece, and then removing the first material from the top surfaces, leaving the first material on the gate electrode sides. The spacer has sloped sidewalls which is advantageous because the sloped sidewalls prevent voids from forming in a subsequent array top oxide deposition step. Spacers may be formed in both the array region, adjacent the gate electrode sides, and also in the support region, at the edges of the isolation trenches.
In one embodiment, a method of forming replacement spacers of a semiconductor device having topographical features and temporary spacers adjacent the topographical features is disclosed, wherein the topographical features include top surfaces and vertical surfaces. The method includes removing the temporary spacers, depositing a permanent spacer material over the semiconductor device topographical features, and removing the permanent spacer material from the topographical feature top surfaces, leaving permanent spacers adjacent vertical surfaces of the topographical features.
In another embodiment, a method of forming a memory device includes providing a workpiece, forming a pad nitride over the workpiece, and forming a plurality of trenches within the workpiece and pad nitride. A capacitor is formed within each trench, and a trench top oxide is formed over the trench capacitors. A gate electrode is formed over the trench top oxide, and a gate electrode contact is formed over the gate electrode. The gate electrode contact has a smaller width than the gate electrode, and the gate electrode contact is separated from the workpiece by a temporary nitride spacer disposed over the gate electrode. The temporary nitride spacer and pad nitride are removed from the workpiece, leaving the top of the workpiece exposed and a divot adjacent the gate electrode contact. A spacer material is deposited over exposed portions of the workpiece and gate electrode and over the top and sides of the gate electrode contact, at least filling the divot, and the spacer material is removed from the top surface of the workpiece and the top of the gate electrode contacts, leaving a portion of the spacer material comprising a spacer on the sides of the gate electrode contact.
Also disclosed is a method of manufacturing a vertical DRAM device, comprising providing a workpiece, forming a pad nitride over the workpiece, forming deep trenches within the workpiece and pad nitride, and forming a memory cell within each deep trench. The memory cell includes a gate electrode disposed near the top of each deep trench and a gate electrode contact adjacent each gate electrode. The gate electrode contact has a smaller width than the gate electrode, and the gate electrode contact is separated from the workpiece by a temporary nitride spacer disposed over the gate electrode. The method includes removing the pad nitride and temporary nitride spacer, depositing a nitrid
Hummler Klaus M.
Scholz Arnd R.
Infineon - Technologies AG
Le D
Slater & Matsil LLP
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