Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-14
2002-08-06
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S321000
Reexamination Certificate
active
06429072
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor memory cell structure having a floating gate.
A conventional structure of a flash memory will be described.
FIG. 1A
is a fragmentary plan view illustrative of a conventional flash memory.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of a conventional flash memory taken along an A—A′ line of FIG.
1
A. The flash memory has an alignment of memory cells
241
which has the following structure. A floating gate
203
is formed over a gate insulation film
202
over a semiconductor substrate
201
. The floating gate
203
is T-shaped which comprises an upper portion and a lower portion, wherein the upper portion laterally extends from the opposite edges of a lower portion to form the T-shaped floating gate
203
. The structure of the memory cell
241
will be described in detail with reference to FIG.
1
B.
Field oxide films
206
are selectively formed on a semiconductor substrate
201
to define an active region or a device region of the semiconductor substrate
201
. Source and drain regions
204
and
205
are selectively formed in the active region or the device region of the semiconductor substrate
201
, whereby a channel region is defined between the source and drain regions
204
and
205
. A gate insulation film
202
is formed on the channel region of the semiconductor substrate
201
. Source side and drain side interconnections
204
a
and
205
a
are formed on the source and drain regions
204
and
205
, wherein the source side and drain side interconnections
204
a
and
205
a
are made of polysilicon films doped with an impurity. In the memory cell
241
, the source and drain
204
and
205
serve as parts of bit lines. The formation of the source side and drain side interconnections
204
a
and
205
a
on and in contact with the source and drain regions
204
and
205
results in reduction in resistance of the source and drain
204
and
205
. A floating gate
203
is formed which comprises an lower part and an upper part. The upper part extends laterally from the opposite edges of the lower part so that the floating gate
203
is T-shaped. The lower part of the floating gate
203
is positioned on the gate insulation film
202
. Side wall oxide films
213
are formed on opposite side walls of the lower part of the floating gate
203
. Insulation films
216
are formed over the field oxide films
206
and the source side and drain side interconnections
204
a
and
205
a
as well as over the side wall oxide films
213
. The upper portion of the floating gate
203
extends over the lower part thereof and the insulation films
216
, so that opposite edges of the upper portion of the floating gate
203
are almost aligned to the edges of the source side and drain side interconnections
204
a
and
205
a
in plane view. An insulation film
207
made of ONO is formed on the upper portion of the floating gate
203
and on the insulation films
216
. A control gate
208
is formed on the insulation film
207
so that the floating gate
203
is separated and electrically floated from the control gate
208
and whereby the floating gate
203
is completely surrounded by the insulation materials to be floated in the memory cell. The control gate
208
serves as a part of a word line in the memory. The above T-shape of the floating gate increases a capacitance thereof.
The source and drain
204
and
205
are commonly used for a plurality of the memory cells
241
. The drain
05
is used as a part of the bit line so that a single bit contact is formed for the plural memory cells
241
so as to allow narrowing the distance between the memory cells, thereby reducing the cell size.
The following descriptions will focus onto the fabrication method of the above flash memory.
FIGS. 2A through 2H
are fragmentary cross sectional elevation views illustrative of a conventional method of forming a memory cell structure over a semiconductor substrate of a flash memory shown in
FIGS. 1A and 1B
.
With reference to
FIG. 2A
, a thin insulation film
202
a
is formed on a surface of a semiconductor substrate
201
. A bottom floating gate part
203
a
is selectively formed on a predetermined region of the thin insulation film
202
a
, wherein a film of a electrode material such as an impurity doped polysilicon is entirely formed on the surface of the semiconductor substrate
201
before patterning the same to form the bottom floating gate part
203
a
. The bottom floating gate part
203
a
is used as a mask for carrying out an ion-implantation into selected upper regions of the semiconductor substrate
201
, whereby source and drain regions
204
and
205
are formed with a self-alignment technique in the selected upper regions of the semiconductor substrate
201
.
With reference to
FIG. 2B
, the thin insulation film
202
a
is removed except for its underlying part which underlies the bottom floating gate part
203
a
, whereby the remaining underlying part of the thin insulation film
202
a
serves as a gate insulation film
202
. An insulation film is entirely formed on the source and drain regions
204
and
205
as well as on opposite side walls and a top surface of the bottom floating gate part
203
a
before an etch back process using a dry etching technique so that the insulation film remain only on the opposite side walls of the bottom floating gate part
203
a
, whereby the side wall insulation films
213
are formed on the opposite side walls of the bottom floating gate part
203
a.
With reference to
FIG. 2C
, an impurity doped polysilicon film is entirely deposited over the source and drain regions
204
and
205
and the side wall insulation films
213
and the bottom floating gate part
203
a
. An etch back process is carried out to the impurity doped polysilicon film until the top of the bottom floating gate part
203
a
is shown, whereby conductive films
214
are formed on the source and drain regions
204
and
205
and positioned outside the side wall insulation films
213
.
With reference to
FIG. 2D
, parts of the conductive films
214
on isolation regions are selectively removed. Grooves are further formed on the isolation region in the semiconductor substrate
201
. An insulation material such as silicon oxide is buried within the grooves, whereby field oxide films
206
are then formed on the isolation regions. As a result, outside edges of the conductive films
214
are defined by inside boundaries of the field oxide films
206
, whereby source side and drain side interconnections
204
a
and
205
a
are formed.
With reference to
FIG. 2E
, an insulation film
216
is entirely formed over the field oxide films
206
, the source side and drain side interconnections
204
a
and
205
a
and the bottom floating gate part
203
a.
With reference to
FIG. 2F
, an overlying part of the insulation film
216
overlying the bottom floating gate part
203
a
is selectively removed by patterning the insulation film
216
with use of a photo-lithography and a subsequent dry etching technique, whereby the top of the bottom floating gate part
203
a
is shown.
With reference to
FIG. 2G
, an impurity doped polysilicon film is entirely formed which extends over the insulation films
216
and the bottom floating gate part
203
a
. The impurity doped polysilicon film is then patterned with a photo-lithography and a subsequent dry etching technique, whereby a top floating gate part
203
b
is formed which extends over the top of the bottom floating gate part
203
a
and inside parts of the insulation films
216
so that opposite edges of the top floating gate part
203
b
are aligned to outside edges of the source side and drain side interconnections
204
a
and
205
a
. As a result, a combination of the top floating gate part
203
b
and the bottom floating gate part
203
a
forms a T-shaped floating gate
203
.
With reference to
FIG. 2H
, an insulation film
207
made of ONO is formed on the top floating gate part
203
b
of the floating gate
203
NEC Corporation
Young & Thompson
LandOfFree
Method of forming a floating gate memory cell structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a floating gate memory cell structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a floating gate memory cell structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2899766