Method of forming a floating gate for a stacked gate flash...

Details Method of forming a floating gate for a stacked gate flash... Method of forming a floating gate for a stacked gate flash...

2005-07-12

2005-07-12

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S778000, C438S942000

Reexamination Certificate

active

06916708

ABSTRACT:
A new method to form a floating gate for a flash memory device is achieved. The method comprises forming a first conductor layer overlying a substrate with a gate dielectric layer therebetween. A masking layer is deposited overlying the first conductor layer. The masking layer is patterned to expose first regions of and to cover second regions of the first conductor layer. A plurality of first concave surfaces are formed on the first conductor layer first regions. The masking layer is removed. A plurality of second concave surfaces are formed on the first conductor layer second regions. The first conductor layer is patterned to form floating gates. The interfaces between the plurality of first and second concave surfaces form vertical tips on the floating gates. A method to form an electron emitter is also disclosed.

REFERENCES:
patent: 6165845 (2000-12-01), Hsieh et al.
patent: 6171906 (2001-01-01), Hsieh et al.
patent: 6479859 (2002-11-01), Hsieh et al.
patent: 6528844 (2003-03-01), Hopper et al.
patent: 6537869 (2003-03-01), Furuhata
patent: 6573153 (2003-06-01), Maeda
patent: 6656854 (2003-12-01), Miyano et al.

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