Method of forming a field effect transistors with a...

Details Method of forming a field effect transistors with a... Method of forming a field effect transistors with a...

2011-07-05

2011-07-05

Chen, Jack (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S585000, C257SE21542

Reexamination Certificate

active

07972916

ABSTRACT:
The process forms a FET with a channel region that has in plane compressive stress in one direction and in plane tensile stress in a perpendicular direction. The process deposits a germanium silicon sacrificial stressor layer on a silicon substrate so that the germanium silicon is in a state of compressive stress. Etching trenches forms silicon pillars covered by the stressor layer and transfers tensile strain to the upper portion of the pillar. The process fills the trenches with stiff insulating material to maintain the strain in the pillar and etching removes the stressor layer. More etching creates recesses on either side of a channel region in the upper portion of the pillar. Doped germanium silicon layers fill the recesses, apply lateral compressive stress to the pillar's channel region and act as source and drain electrodes. A gate is formed above the strained channel region.

REFERENCES:
patent: 7338834 (2008-03-01), Clifton
Shyam Gannavaram, “Low Temperature (≦800 ° C.) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for Sub-70 nm CMOS,” 2000 IEEE Xplore, IEDM 00-437-440.
Scott E. Thompson, et al. “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions of Electron Devices, vol. 51, No. 11, Nov. 2004.

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