Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-12-18
2004-11-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S329000, C257S330000, C257S390000, C438S243000, C438S268000, C438S316000
Reexamination Certificate
active
06818513
ABSTRACT:
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK
NOT APPLICABLE
BACKGROUND OF THE INVENTION
Embodiments of the invention relate to field effect transistors such as MOSFET (metal oxide semiconductor field effect transistor) devices and methods for making field effect transistors.
Power MOSFET devices are well known and are used in many applications. Exemplary applications include automotive electronics, portable electronics, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its drain-to-source on-state resistance (R
DS(on)
), which is defined as the total resistance encountered by a drain current. R
DS(on)
is proportional to the amount of power consumed while the MOSFET device is on. In a vertical power MOSFET device, this total resistance is composed of several resistive components including an inversion channel resistance (“channel resistance”), a starting substrate resistance, an epitaxial portion resistance and other resistances. The epitaxial portion is typically in the form of a layer and may be referred to as an “epilayer”. R
DS(on)
can be reduced in a MOSFET device by reducing the resistance of one or more of these MOSFET device components.
Reducing R
DS(on)
is desirable. For example, reducing R
DS(on)
for a MOSFET device reduces its power consumption and also cuts down on wasteful heat dissipation. The reduction of R
DS(on)
for a MOSFET device preferably takes place without detrimentally impacting other MOSFET characteristics such as the maximum breakdown voltage (BV
DSS
) of the device. At the maximum breakdown voltage, a reverse-biased epilayer/well diode in a MOSFET breaks down resulting in significant and uncontrolled current flowing between the source and drain.
It is also desirable to maximize the breakdown voltage for a MOSFET device without increasing R
DS(on)
. The breakdown voltage for a MOSFET device can be increased, for example, by increasing the resistivity of the epilayer or increasing the thickness of the epilayer. However, increasing the epilayer thickness or the epilayer resistivity undesirably increases R
DS(on)
.
It would be desirable to provide for a MOSFET device with a high breakdown voltage and a low R
DS(on)
. Embodiments of the invention address this and other problems.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the invention are directed to MOSFET devices and methods of manufacture. The MOSFET devices have a low R
DS(on)
and have a high breakdown voltage. For example, with the current state of the art, in embodiments of the invention, R
DS(on)
for an exemplary 200 V N-channel trench MOSFET can be reduced by 80% as compared to a conventional 200 V N-channel trench MOSFET while maintaining a high breakdown voltage.
One embodiment of the invention is directed to a method of forming a field effect transistor device comprising: forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region; forming a source region of the first conductivity type in the well region; forming a trench gate electrode adjacent to the source region; forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and depositing a semiconductor material of the second conductivity type within the stripe trench.
Another embodiment of the invention is directed to a method of forming a field effect transistor device comprising: a) forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type having a major surface and a drain region; b) forming a source region of the first conductivity type formed in the well region; c) forming a gate electrode adjacent to the source region; d) forming a stripe trench extending from the major surface of the semiconductor substrate into the semiconductor substrate to a predetermined depth; and e) depositing a semiconductor material of the second conductivity type within the stripe trench, wherein at least one of steps a), b), and c) occurs after step e).
These and other embodiments of the invention are described in greater detail below with reference to the appended drawings.
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Fairchild Semiconductor Corporation
Nelms David
Nguyen Dao H.
Townsend and Townsend / and Crew LLP
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