Method of forming a field effect transistor and method of formin

Details Method of forming a field effect transistor and method of formin Method of forming a field effect transistor and method of formin

1996-09-20

1999-04-27

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438231, H01L 21336

Patent

active

058973575

ABSTRACT:
A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impurity from the respective pairs of polysilicon projections into the semiconductor substrate to provide respective NMOS and PMOS type diffusion regions within the substrate adjacent the respective first and second gate lines. A combination of blanket doping and masked doping to produce the respective NMOS and PMOS type diffusion regions is also contemplated. The invention also has utility to formation of only one of NMOS or PMOS type field effect transistors, as opposed to CMOS formation.

REFERENCES:
patent: 4330931 (1982-05-01), Liu
patent: 4356622 (1982-11-01), Widmann
patent: 4494997 (1985-01-01), Lemnios et al.
patent: 4824796 (1989-04-01), Chiu et al.
patent: 4945070 (1990-07-01), Hsu
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5015594 (1991-05-01), Chu et al.
patent: 5112761 (1992-05-01), Matthews
patent: 5200352 (1993-04-01), Pfiester
patent: 5266517 (1993-11-01), Smayling et al.
patent: 5283200 (1994-02-01), Okamoto
patent: 5395787 (1995-03-01), Lee et al.
patent: 5422289 (1995-06-01), Pierce
patent: 5571733 (1996-11-01), Wu et al.
Michel, A.E., et al., "Ion-Implanted Polysilicon Diffusion Sources", Nuclear Instruments and Methods, North-Holland Publishing Company, 1983, pp. 700-714.
Kusters, K.H. et al., "A Self Aligned Contact Process With Improved Surface Planarization", Journal De Physique, No. C4, Sep. 1988, pp. 603-506.

Affiliated with

Also associated with

Rating

Method of forming a field effect transistor and method of formin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a field effect transistor and method of formin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a field effect transistor and method of formin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-681051