Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-02
2001-02-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S250000, C438S253000, C438S393000, C438S396000
Reexamination Certificate
active
06190957
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus having an array of memory cells each comprising complex oxides for forming an insulation film of an information storing capacitor thereof and a manufacturing method therefor, and more particularly to structures of a wiring portion for connecting a cell transistor and a cell capacitor, a contact portion of a bit line and a memory cell in a ferroelectric random access memory (FRAM) having a ferroelectric insulation film for a capacitor and a method of forming the same, and to a structure of a memory cell of a dynamic random access memory (DRAM) having an array of dynamic memory cells having a capacitor insulation film made of dielectric material and a method of forming the same.
In recent years, a non-volatile ferroelectric memory cell (a FRAM cell) and a FRAM having the foregoing memory cell array comprising, as an interelectrode insulation film of a capacitor for storing information, a ferroelectric thin film made of a material having a perovskite structure or a layered perovskite structure have attracted attention.
The ferroelectric film has a characteristic such that electric polarization generated once when an electric field has been applied is retained even if the electric field is removed and the direction of the polarization is inverted when an electric field having intensity exceeding a certain level is applied into a direction opposite to the direction of the foregoing electric field.
Taking notice of the characteristic of the dielectric material for inverting the direction of polarization, a technique has been developed to realize a FRAM cell by employing a ferroelectric material to form an insulation film of an information storing capacitor of a memory cell.
The FRAM cell has a structure in which a ferroelectric capacitor is substituted for a capacitor of a DRAM cell. The FRAM employs a method (a data destructive reading method) in which a charge in a polarization switched or non-switched state is fetched from a ferroelectric capacitor through a switching MOS transistor. Thus, the FRAM has a characteristic that data written and stored on a memory cell is not lost even if the operating power source is turned off.
The FRAM, which is the non-volatile memory, has a characteristic such that the FRAM does not require a refreshing operation to store data and no electric power is-required in a standby mode, as compared with the DRAM which is a representative large-capacity memory. When the FRAM is compared with a flash memory, which is another non-volatile memory, the FRAM has a characteristic that a great number of data rewriting times is permitted and data can significantly quickly be rewritten. When the FRAM is compared with a SRAM (Static Random Access Memory) which is used in a memory card or the like and which is needed to be backed up by a battery, the FRAM has characteristics that the electric power consumption can be reduced and the area of the cell can significantly be reduced.
The FRAM having the above-mentioned characteristics are significantly expected to be substituted for the conventional DRAM, the flash memory and the SRAM and applied to a logic circuit consolidation device and the like. Since the FRAM is able to operate at high speed without any battery, development to a non-contact ID card (RF-ID: Radio Frequency-Identification Data) has been commenced.
The structure of the memory cell in the FRAM is classified into two main types. One of the structures is arranged such that a ferroelectric film is, in place of a para-electric film, used to form a storage capacity which is as well as employed in the DRAM and which is arranged to store a charge capacity serving as information. Another structure is arranged such that a ferroelectric film is, in place of a silicon oxide film, employed to form a gate insulation film of the MOSFET. The latter structure, having no appropriate ferroelectric film which can directly be formed on a silicon layer, cannot practically be used. Since the latter structure has simply been suggested until today, the FRAM is usually the former structure.
The FRAM cell includes a 1-transistor/1-capacitor (abbreviated to 1T/1C) structure composed of one transistor Q and one ferroelectric capacitor C as shown in
FIG. 1 and a
2-transistor/2-capacitor (abbreviated to 2T/2C) structure composed of two transistors Q
1
and Q
2
and two ferroelectric capacitors C
1
and C
2
, for example, as shown in FIG.
3
A.
Although the 1T/1C structure has an advantage in that a dense integration similarly to the DRAM is permitted, variation of the ferroelectric characteristics of the memory cells and variation of deterioration must be prevented in order to realize memory cells capable of preventing variation of their characteristics. Thus, the foregoing structure has a problem in that the manufacturing yield and the reliability as the device cannot easily be improved.
Although the 2T/2C structure has a problem in that an area which is two times the area required for the 1T/1C is required, a great characteristic margin is permitted and thus the manufacturing yield and the reliability as the device can be improved.
Both of the foregoing structures are formed such that a stacked structure of an electrode/ferroelectric member/electrode is formed on the base insulation film, Al or Cu wiring is performed through a contact hole formed in the oxide film on the stacked structure, and a passivation film is formed to serve as a protective film.
Since the FRAM cell is able to operate at high speed with small electric power consumption and a highly integrated structure is expected as described above, the reduction of the area for the memory cells and a manufacturing process which does not considerably deteriorate the ferroelectric member must be realized. Moreover, a multilayer wiring technique has not been established which is required when the conventional FRAM is consolidated with another device or when a highly integrated structure is formed.
The reason why the semiconductor integrated circuit having the FRAM device mounted thereon cannot easily be formed into a multilayered wiring structure is that the ferroelectric material has a low tolerance to a reducing atmosphere (in particular, a hydrogen atmosphere). Since the conventional LSI processes almost include a process in which hydrogen is mixed, a critical problem arises when the FRAM is manufactured.
As an example of the process in which hydrogen is mixed, a process for plugging a via hole in a multilayered wiring structure is exemplified. As a method of embedding a via hole having a large aspect ratio, a process for embedding tungsten by a CVD method is usually employed. Since the process for embedding tungsten encounters generation of a multiplicity of hydrogen groups, the ferroelectric is damaged critically.
The foregoing problem will specifically be described.
Hitherto, the ferroelectric memory cell has been formed by (1) a structure in which a bit line is formed later such that a ferroelectric capacitor is formed below the bit line; and (2) a structure in which the bit line is formed previously such that the bit line is formed below the ferroelectric capacitor.
When the ferroelectric memory cell is manufactured which has the structure in which the bit line is formed later, the ferroelectric capacitor is formed on a switching MOS transistor. Then, a lower electrode of the ferroelectric capacitor and the MOS transistor are connected to each other by a polysilicon plug, and then the bit line is formed on the ferroelectric capacitor.
When the ferroelectric capacitor is formed, the lower electrode of the ferroelectric capacitor is formed by, usually, using Pt (platinum) on the polysilicon plug, followed by forming the ferroelectric thin film. When the ferroelectric thin film is crystallized, oxidation annealing at high temperatures must be performed.
When PZT (lead-zirconate-titanate) is employed as the ferroelectric material, a defect caused from diffusion of Pb in the PZT occurring due to insufficient oxidation results in deter
Hidaka Osamu
Kanaya Hiroyuki
Kunishima Iwao
Mochizuki Hiroshi
Okuwada Kumi
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Kennedy Jennifer M.
Niebling John F.
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