Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-03-18
2004-10-19
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S637000, C438S638000
Reexamination Certificate
active
06806203
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. Some specific embodiments of the invention pertain to a method for forming a dual damascene structure in an integrated circuit in which the etched dielectric layer(s) include one or more porous low dielectric constant films.
As semiconductor device sizes have become smaller and integration density increases, many issues have become of increasing concern to semiconductor manufacturers. One such issue is that of interlevel “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to better isolate them from each other.
Another such issue is the “RC time constant” of a particular trace. Each conductive trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
Hence, in order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators that have a lower dielectric constant than the insulators of previous generations of integrated circuits. To this end, semiconductor manufacturers, materials suppliers and research organizations among others have been researching and developing materials for use as premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers in integrated circuits that have a dielectric constant (k) below that of silicon dioxide (generally between about 3.9-4.2) and below that of fluorine-doped silicate glass (FSG, generally between about 3.4-3.7). These efforts have resulted in the development of a variety of low dielectric constant films (low k films). As used herein, low k films are those having a dielectric constant less than about 3.0 including films having a dielectric constant below 2.0.
Some approaches to developing such low k films include introducing porosity into known dielectric materials to reduce the material's dielectric constant. Dielectric films when made porous, tend to have lower dielectric constants (the dielectric constant of air is normally 1.0). One particular class of porous low k films includes ordered mesoporous silica materials. One known method of forming such ordered mesoporous silica films is referred to as the sol gel process, in which high porosity films are produced by hydrolysis and polycondensation of a metal oxide.
The sol gel process is a versatile solution process for making ceramic material. In general, the sol gel process involves the transition of a system from a liquid “sol” (mostly colloidal) into a solid “gel” phase. The starting materials used in the preparation of the “sol” are usually inorganic metal salts or metal organic compounds such as metal alkoxides. The precursor solutions are typically deposited on a substrate by spin on methods. In a typical sol gel process, the precursor is subjected to a series of hydrolysis and polymerization reactions to form a colloidal suspension, or a “sol.” Further processing of the “sol” enables one to make ceramic materials in different forms. One method of forming such mesoporous low k films is described in U.S. application Ser. No. 09/823,932, filed on Mar. 29, 2001 in the name of Robert P. Mandel et al. and assigned to Applied Materials, Inc., the assignee of the present case. The Ser. No. 09/823,932 application is hereby incorporated by reference in its entirety.
Concurrent with the move to intermetal dielectric layers having a dielectric constant lower than silicon dioxide, many semiconductor manufacturers are using copper rather than aluminum in the formation of their multilevel interconnect structures. Because copper is difficult to etch in a precise pattern, however, the traditional deposition/selective etch process used for forming such interconnects has become disfavored. Accordingly, a process referred to as a dual damascene process, is used by many semiconductor manufacturers to form copper interconnects. In a dual damascene process, one or more blanket intermetal dielectric layers are deposited and then subsequently patterned and etched to define both the interlayer vias and the interconnect lines. Copper or another conductive material is then inlaid into the defined pattern and any excess conductive material is removed from the top of the structure in a planarization process, such as a chemical mechanical polishing (CMP) process.
The etching of the dielectric layer in such a dual damascene process typically includes two separate lithography steps. One step defines the trenches and another the vias. Photoresist and organic bottom antireflective coating (BARC) films have been found to penetrate the pores of porous low k films so dual damascene lithography techniques for porous low k films typically include the use of a hard mask between the ELK material and the photoresist. One such scheme that has been proposed includes the use of two separate hard masks as shown in
FIGS. 1
a
through
1
h.
FIGS. 1
a
through
1
h
illustrate one method used in the fabrication of a trench-first dual damascene scheme using a silicon-containing dielectric layer
10
formed over a substrate
2
. Substrate
2
may include an already formed conductive line
4
, e.g., a copper line, a surrounding dielectric material
6
and a barrier layer separating the two. Dielectric layer
10
may be a single layer or a multilayer dielectric stack. Dielectric layer
10
shown in
FIG. 1
a
includes multiple layers: a barrier layer
12
, a via dielectric layer
14
and a porous low k layer
16
. Formed over dielectric layer
10
are a first hard mask layer
20
, a second hard mask layer
22
, a bottom antireflective coating
24
and a photoresist layer
30
. In some prior processes known to the inventors where the trench and via portion of underlying dielectric layer
10
are a silicon-containing material, hard mask layer
22
is a silicon nitride or similar layer and layer
20
is a silicon carbide (SiC or SiCN) or similar layer.
As shown in
FIG. 1
a
photoresist layer
30
is patterned and etched using a metal wiring pattern to form an opening
32
. The metal wiring pattern is then transferred into hard mask layer
22
using an appropriate etching process (
FIG. 1
b
). Any remaining photoresist layer
30
is then stripped along with antireflective coating
24
(
FIG. 1
c
). Next, a new bottom antireflective coating
40
and photoresist layer
42
is formed over the substrate such that antireflective coating
40
fills in etched opening
32
(
FIG. 1
d
).
As shown in
FIG. 1
d
, photoresist layer
42
is then patterned and etched according to a via pattern to form an opening
34
. The via pattern is then transferred into dielectric stack
10
using photoresist layer
42
as the p
Bekiaris Nikolaos
Chang Josephine
Nguyen Phong H.
Weidman Timothy
Applied Materials Inc.
Everhart Caridad
Rocchegiani Renzo
Townsend and Townsend and Crew
LandOfFree
Method of forming a dual damascene structure using an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a dual damascene structure using an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a dual damascene structure using an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3330314