Method of forming a DRAM cylinder shaped capacitor

Details Method of forming a DRAM cylinder shaped capacitor Method of forming a DRAM cylinder shaped capacitor

1998-03-26

2001-01-09

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S253000, C438S396000, C438S397000, C438S694000, C438S713000, C438S723000, C438S724000, C438S978000

Reexamination Certificate

active

06171902

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device represented by a DRAM (Dynamic Random Access Memory), and to a manufacturing method thereof.
2. Description of the Related Art
In recent years, more downsizing and a higher integration of a semiconductor device have been tried for their attainment, and, therewith, individual device elements such as wiring etc have been increasingly made hyperfine. From such a trend, however, when forming, e.g., a contact hole, it becomes impossible to ensure a sufficient allowance in alignment between the contact hole and an electrode (a conductive part) of a lower layer due to the hyperfine structure. Hence, there has been adopted a method by which after the contact hole has been formed normally by a self-alignment or so formed as to have a large aperture, a side-wall is formed of an insulating layer within this contact hole, and the alignment allowance is taken by substantially reducing the contact hole.
Further, in the case of a DRAM as a semiconductor device, with a reduced cell area due to the hyperfine structure, as shown in FIG.
3
(
g
), there has been adopted a so-called cylinder type electrode structure in which a capacitor electrode is formed upright enough to obtain a larger surface area.
For forming this cylinder type electrode structure, as illustrated in FIG.
3
(
a
), a contact hole
2
is formed with an aperture within an inter-layer insulating layer
1
, and thereafter polysilicon
3
is deposited inwardly of the contact hole
2
so that the contact hole
2
is filled with the polysilicon
3
. Note that the reference numeral
8
designates a gate electrode, and
7
represents a silicon nitride layer. Subsequently, the polysilicon
3
is etched-back with the result that, as shown in FIG.
3
(
b
), only the polysilicon
3
a
embedded into the contact hole
2
is left. Subsequently, the silicon oxide layer is deposited on the entire surface, and further this is subjected to patterning, thereby forming a recessed portion
4
for forming a cylinder as illustrated in FIG.
3
(
c
).
Then, as shown in FIG.
3
(
d
), side polysilicon
5
is deposited over the whole surface, and subsequently a silicon oxide layer is deposited thereon. Then, this silicon oxide layer is etched-back and thus left only in the recessed portion
4
as shown in FIG.
3
(
e
).
Next, the polysilicon
5
is partially removed by etching it back, thereby forming a bottomed cylindrical polysilicon
5
a
as illustrated in FIG.
3
(
f
). Thereafter, a silicon oxide layer
6
left in the recessed portion
4
and the silicon oxide layer forming the recessed portion
4
are removed by etching, thereby obtaining a cylinder type electrode structure shown in FIG.
3
(
g
), i.e., a lower electrode structure of a cylinder type capacitor.
Incidentally, according to the cylinder type electrode structure, the side-wall
7
is formed in order to substantially reduce the contact hole
2
. This side-wall
7
, however, generally involves the use of a silicon nitride layer (SiN) exhibiting a high covering property even in a minute hole.
In the case of using the silicon nitride layer as the side-wall
7
, however, as shown in FIG.
3
(
h
), if a contact deviation occurs, it follows that the side-wall
7
comes into a direct contact with a gate electrode
8
and a field edge (unillustrated). Consequently, there arises such an inconvenience that a transistor characteristic fluctuates due to a stress in the silicon nitride layer, hydrogen in this layer and further an interface level etc, or that a junction leak current increases.
Moreover, in the DRAM having the above cylinder type electrode structure, the polysilicon
3
a
embedded into the contact hole
2
and the polysilicon
5
a
constituting a part of the cylinder portion are separately formed and hence microscopically discontinuous. Therefore, there might be a possibility in which the polysilicon
5
a
becoming a lower electrode of the cylinder type capacitor in the cylinder type electrode structure exfoliated from the contact composed of the polysilicon
3
a
embedded into the contact hole
2
when in, e.g., cleaning and spin-dry processes.
Furthermore, the manufacturing method of the above cylinder type electrode structure presents a drawback to be ameliorated, wherein the manufacturing process is complicated such as depositing the polysilicon twice.
SUMMARY OF THE INVENTION
It is a primary object of the present invention, which was contrived under such circumstances, to provide a semiconductor device and a manufacturing method thereof that are capable of further advancing a hyperfine structure by obviating such an inconvenience that a side-wall composed of a silicon nitride layer used in a contact hole contacts a gate electrode etc due to an alignment deviation, and a semiconductor device and a manufacturing method thereof that are capable of simplifying a manufacturing process as well as of obviating such an inconvenience that a lower electrode of a cylinder type capacitor is exfoliated from a contact within a contact hole.
To accomplish the above object, according to a first aspect of the present invention, a semiconductor device constructed such that a contact hole is formed in an inter-layer insulating layer, a side-wall is formed along a wall surface within the contact hole and has its bottom composed of a silicon oxide layer or a silicon oxide nitride layer, and an upper portion of the silicon oxide layer or the silicon oxide nitride layer is formed of a silicon nitride layer.
According to this semiconductor device, the bottom of the side-wall is composed of the silicon oxide layer or the silicon oxide nitride layer. The side-wall bottom is composed of the silicon oxide layer or the silicon oxide nitride layer, and accordingly the portion contacting the gate electrode is formed of the silicon oxide layer or the silicon oxide nitride layer. Therefore, even if the side-wall comes into a direct contact with the gate electrode, the silicon nitride layer existing on the upper portion of the silicon oxide layer or the silicon oxide nitride layer does not directly contact the gate electrode.
According to a second aspect of the present invention, a method of manufacturing a semiconductor device comprises a step of forming a contact hole in an inter-layer insulating layer on a silicon substrate, which communicates with the silicon substrate, a step of next forming a silicon oxide layer or a silicon oxide nitride layer on a surface of the silicon substrate that faces inwardly of the contact hole, a step of subsequently forming a silicon nitride layer over an entire surface on the silicon substrate, and a step of thereafter executing an anisotropic etching process on the silicon nitride layer, executing the anisotropic etching process on the silicon oxide layer or the silicon oxide nitride layer on the surface of the silicon substrate within the contact hole, and thereby forming a side-wall composed of a silicon nitride layer and a silicon oxide layer or a silicon oxide nitride layer within the contact hole.
According to this manufacturing method, the silicon oxide layer or the silicon oxide nitride layer is provided on the surface of the silicon substrate that faces inwardly of the contact hole. Further, after forming the silicon nitride layer over the entire surface, the side-wall composed of the silicon nitride layer and the silicon oxide layer or the silicon oxide nitride layer is formed within the contact hole by executing the anisotropic etching process on the silicon nitride layer and the silicon oxide layer or the silicon oxide nitride layer. Therefore, even if the contact deviation occurs with the result that the gate electrode faces inwardly of the contact hole, because of the silicon nitride layer being formed after the silicon oxide layer or the silicon oxide nitride layer has been formed within the contact hole, there is eliminated a possibility in which the silicon nitride layer forming the side-wall does not directly contact the gate electrode.
According to a

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