Method of forming a deep trench DRAM cell

Details Method of forming a deep trench DRAM cell Method of forming a deep trench DRAM cell

2001-10-30

2004-05-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S386000, C438S387000

Reexamination Certificate

active

06737316

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a deep trench DRAM process and, more particularly, to a method of forming a deep trench DRAM device to achieve the desired characteristics of low capacitance, smaller cell size, high functionality and simplified manufacturing process.
2. Description of the Related Art
DRAM devices are widely applied in integrated circuits technology, in which a DRAM cell typically consists of a storage capacitor and an access transistor. There is much interest in reducing the size of DRAM devices to increase their density on an IC chip, thereby reducing size and power consumption of the chip, and allowing faster operation. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. This also causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, an important challenge is to promote storage ability and operating stability of capacitors with decreased scale and increased integration of the DRAM device. A vertical transistor has recently been developed which can maintain the gate length at a suitable value for obtaining low leakage, without decreasing the bit line voltage or increasing the memory cell's lateral dimension. Also, a deep trench capacitor can be fabricated directly below the vertical transistor without consuming any additional wafer area.
U.S. Pat. No. 5,571,730 discloses a deep trench DRAM device with a vertical transistor and a method for manufacturing the same.
FIG. 1
is a top view showing the DRAM cell, wherein reference symbol WL indicates a wordline, T indicates a transistor, BC indicates a bitline contact hole, BL
1
indicates a first bitline, and BL
2
indicates a second bitline. The transistor T is formed in a shape extended in the wordline direction, and the bitline contact hole BC is located to one side of the center of the transistor T in the wordline direction. Multi-layered bitlines are formed, so that adjacent transistors T in the wordline direction are connected with the first bitline BL
1
and the second bitline BL
2
, respectively, both of which are located at different heights.
FIGS. 2A
to
2
E are cross-sections along line
2
—
2
in
FIG. 1
showing the conventional method of forming the DRAM cell. As shown in
FIG. 2A
, a first semiconductor substrate
10
is etched to form silicon pillars
12
, and a source region
14
is formed on the top of the pillar
12
. An oxide film
15
is then deposited on the entire surface of the first semiconductor substrate
10
to form a groove in the space in the wordline direction. Next, a nitride film
16
is conformally deposited on the oxide film
15
, and an oxide layer
17
is deposited to completely fill the grooves between pillars
12
. Thereafter, a plurality of first contact holes
18
is formed to expose the source regions
14
, respectively.
As shown in
FIG. 2B
, a conductive material is deposited and patterned to form a capacitor storage electrode
19
connected to the source region
14
through the first contact hole
18
. Thereafter, a dielectric film
20
is deposited on the entire surface of the capacitor storage electrode
19
, and then a plate electrode
21
is deposited on the entire surface of the dielectric film
20
to fill the under-cut portion of the storage capacitor electrode
19
. Thus, a first capacitor C
1
and a second capacitor C
2
are completed. As shown in
FIG. 2C
, a first insulating layer
22
is deposited on the plate electrode
21
, and a new wafer is attached on the first insulating layer
22
by a direct wafer bonding method, thus providing a second semiconductor substrate
24
. Next, after turning the backside of the first semiconductor substrate
10
upward, the backside of first semiconductor substrate
10
is etched until the oxide film
15
is exposed.
As shown in
FIG. 2D
, a drain region
25
is formed on the upper portion of the pillar
12
, and the oxide film
15
is isotropically etched with the nitride film
16
as the etch-blocking layer. Next, a gate insulating film
26
is formed by thermally oxidizing the exposed surface of the pillars
12
. Thereafter, a conductive layer
27
is deposited on the entire surface of the resultant structure. As shown in
FIG. 2E
, the conductive layer
27
is etched to form a gate electrode
28
surrounding the pillar
12
. Thus, the transistors T
1
, T
2
comprised of the source region
14
, the drain region
25
and the gate electrode
28
are completed. Next, after depositing a second insulating layer
29
on the entire surface of the second semiconductor substrate
24
, a first bitline contact hole
30
is formed to expose the drain region
25
of the first transistor T
1
. Thereafter, a conductive layer filling the first bitline contact hole
30
is patterned to serve as a first bit line BL
1
. Next, a third insulating layer
31
is deposited on the entire surface of the second semiconductor substrate
24
, and then a second bitline contact hole
32
is formed to expose the drain region
25
of the second transistor T
2
. Finally, a conductive layer filling the second bitline contact hole
32
is patterned to serve as a second bit line BL
2
.
However, in the above-described method for manufacturing the DRAM cell, the structures of the deep trench capacitor, the collar structure and the source region
14
are formed on the front side of first substrate
10
, and then reversed to attach the second substrate
24
. The other structures of gate electrode
28
, drain region
25
, and vertical channel are formed on the back side of the first substrate
10
. This complicated process increases process time and production cost. Thus, a simple deep trench DRAM process solving the aforementioned problems is called for.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a deep trench DRAM cell, preferably a sub-150 nm DRAM device, to achieve the desired characteristics of low capacitance, smaller cell size, high functionality and simple collar process.
A method of forming a deep trench DRAM cell is performed on a semiconductor substrate, which has a collar oxide plate and a plurality of deep trenches passing through the collar oxide plate and the substrate to a predetermined depth. First, a deep trench capacitor is formed in each deep trench, wherein the deep trench capacitor has an ion diffusion region with a second conductive type in the substrate surrounding the deep trench, a dielectric layer on the sidewall and bottom of the deep trench, and a first doped polysilicon layer filling the deep trench. Then, using SOI technology, a silicon layer is formed on the planarized surface of the collar oxide plate and the first doped polysilicon layer. Next, a first ion-diffusion layer is formed on the top of the silicon layer. Next, the ion-diffusion layer and the silicon layer on the collar oxide plate are removed to form a plurality of pillars. Then, an oxide layer is formed on the entire surface of the first doped polysilicon layer. Thereafter, a second ion-diffusion layer is formed on the sidewall of the silicon layer, and then annealing treatment is used to form a third ion-diffusion layer at the bottom of the silicon layer. Next, a nitride liner is formed on the entire surface of the substrate, and a second doped polysilicon layer with the second conductive type is formed on the nitride liner, wherein the top of the second doped polysilicon layer reaches the top of the third ion diffusion region. After oxidizing the second doped polysilicon layer to form an oxidation layer, the exposed region of the nitride liner is removed. Finally, a third doped polysilicon layer is formed on the oxidization layer surrounding each of the pillars.
Accordingly, it is a principal object of the invention to provide a simple process to manufacture a deep trench DRAM cell with a vertical transistor.
It is another object of the invention to provide the collar oxide plate prior to the formation of the deep

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