Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-19
2004-08-03
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S240000, C438S398000, C438S665000
Reexamination Certificate
active
06770528
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present Invention relates to a method of manufacturing a semiconductor integrated circuit device. More particularly, the invention relates to a technique, which is useful and efficient when applied to the process of forming conductive layers in the trenches or through holes made in an insulating film.
BACKGROUND OF THE INVENTION
The memory cells of a DRAM (Dynamic Random Access Memory) are arranged at the intersections of a plurality of word lines and a plurality of bit lines, which are provided on the major surface of the, semiconductor substrate. Hence, the memory cells are arranged in rows and columns on the major surface of the semiconductor substrate. Each of the memory cells comprises a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a capacitive element. The MISFET is turned on to select the memory cell. The capacitive element Is connected to the MISFET in series, for storing data.
Each MISFET for selecting one memory cell is provided in an active region of the substrate, which is surrounded by element-Isolating regions. The cell-selecting MISFET comprises a gate insulating film, a gate electrode formed integral with a word line, and a pair of semiconductor regions serving as the source and the drain, respectively. Each bit line is provided above two adjacent cell-selecting MISFETs and electrically connected to the common source or drain of the adjacent MISFETs, which are arranged along the bit line. The data-storing capacitive element is also located above the MISFETs, too, and electrically connected to the common source or drain of the MISFETs.
Japanese Patent Application Laid-Open Publication No. 7-7084 discloses a DRAM of a stacked capacitor structure, in which data-storing capacitive elements are provided above cell-selecting MISFETs. In the DRAM disclosed in the publication, the lower electrode (data-storing electrode) of each data-storing capacitive element is shaped as a hollow cylinder with a larger surface to compensate for the decrease in stored charge which inevitably results from the size reduction of the memory cell. The upper electrode (plate electrode) of the data-storing capacitive element is provided above the lower electrode.
Japanese Patent Application Laid-Open Publication No. 11-17144 discloses the technique of forming a reinforcing member made of insulating film, on the bottom of a hollow cylindrical lower electrode of the type described above. The reinforcing member increases the mechanical strength of the lower electrode thereby preventing the lower electrode from toppling in the course of manufacturing the data-storing capacitive element.
SUMMARY OF THE INVENTION
The Inventors of the present invention have been developing the technique of first forming a trench in a thick silicon oxide film deposited and located above a bit line and then forming the lower electrode (data-storing electrode) of a data-storing capacitive element in the trench.
The data-storing capacitive element is manufactured as follows. First, a thick silicon oxide film is formed above the bit line. A trench is made In-the silicon oxide film by means of dry etching using a mask made of a photoresist film. Then, a polycrystalline silicon film is deposited in the trench and on the silicon oxide film. Thereafter, a coating is formed on the polycrystalline silicon film by means of SOG (Spin On Glass) or the like, thereby protecting the polycrystalline silicon film. A part of the polycrystalline silicon film, which is provided on the silicon oxide film, is removed by dry etching. The other part of the polycrystalline silicon film, which remains. In the trench, will be used as the lower electrode.
Next, the SOG film Is removed from the polycrystalline silicon film remaining In the trench. The SOG film is removed by dry etching or wet etching based upon the difference In etching rate between the silicon oxide film and the SOG film.
Then, a dielectric film, such as a tantalum oxide (Ta2O5) film, is deposited on the polycrystalline silicon film. A conductive film made of titanium oxide or the like is deposited on the tantalum oxide film. A data-storing capacitive element is thereby manufactured, which comprises a lower electrode made of a polycrystalline silicon film, a capacitance insulating film made of a tantalum oxide film, and an upper electrode made of a titanium oxide film.
The data-storing capacitive element described above has its lower electrode provided in a trench made in a silicon oxide film. Provided in the trench, the lower electrode would not be toppled as the conventional lower electrode that is shaped like a hollow cylinder, in the course of manufacturing the data-storing capacitive element. In view of this, the lower electrode is advantageous over the conventional one. However, the lower electrode of the data-storing capacitive element has a smaller surface than the conventional lower electrode, whose inner surface and outer surface are used as a region to effectively hold the accumulated charge. In order to hold the charge reliably, some measures must be taken to increase the surface area of the lower electrode. To Increase the surface area of the lower electrode, the trench in which the lower electrode is provided may be made deeper, and depressions and projections may be made at the surface of the lower electrode.
However, the method of manufacturing the lower electrode, wherein the selective etching of the SOG film Is achieved based upon the difference in etching rate between the silicon oxide film and the SOG film, is disadvantageous In one respect. Since the difference in etching rate between these films is not sufficiently large, the oxide silicon film outside the trench is etched to some extent when the SOG film covering the polycrystalline silicon film provided In the trench is etched. Consequently, the upper surface of the silicon oxide film lowers, in particular where depressions and projections are made at the surface of the polycrystalline silicon film and over-etching is performed to remove those parts of the SOG film which remain in the depressions and between the projections.
If the upper surface of the silicon oxide film lowers, the upper edge of the polycrystalline silicon film formed in the trench protrudes from the plane in which the trench opens. This impairs the surface smoothness of the data-storing capacitive element such that it is inevitably impaired. Further, an electric field concentrates at the upper edge of the polycrystalline silicon film, which inevitably increases the leakage current of the data-storing capacitive element.
An object of the present invention is to provide a technique for enhancing the manufacturing yield of a DRAM comprising data-storing capacitive elements, each having a lower electrode provided in a trench made in an insulating film.
Another object of the invention is to provide a technique of forming a conductive layer in a trench or a through hole made in an insulating film.
Additional objects and novel features of the invention will be obvious from the description, which follows, and the drawings accompanying the present specification.
The representative embodiments of this invention are briefly described as follows.
(1) A method of manufacturing a semiconductor integrated circuit device, according to this invention, comprises the following steps:
(a) forming a first conductive film on a surface of a semiconductor substrate, forming a first insulating film on the first conductive film, and making a trench or a through hole in the first insulating film;
(b) forming a second conductive film in the trench or the through hole and on the first insulating film, said second conductive film extending through the trench or the through hole and electrically connected to the first conductive film;
(c) covering the second conductive film with a photoresist film and applying exposure light to the photoresist film, thereby exposing to light at least that part of the photoresist film which lies outside the trench or the through hole;
(d) removing a part of the photoresist f
Furukawa Ryouichi
Hiranuma Masayuki
Ishizaka Masayuki
Saitoh Koichi
Shimoda Maki
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Fourson George
Hitachi ULSI Systems Co. Ltd.
Pham Thanh V
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