Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2009-01-07
2010-12-07
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S637000, C438S671000, C438S717000, C438S736000, C438S950000, C257SE21158, C257SE21495, C257SE21597
Reexamination Certificate
active
07846825
ABSTRACT:
In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width.
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Kang Nam-Jung
Ryu So-Hyun
Song Jae-Hoon
Yang Dong-Kwan
Garber Charles D
Mills & Onello LLP
Roman Angel
Samsung Electronics Co,. Ltd.
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