Method of forming a CMOS transistor

Details Method of forming a CMOS transistor Method of forming a CMOS transistor

2000-01-21

2000-10-03

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438232, 438305, 257204, H01L 218238

Patent

active

061272124

ABSTRACT:
The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer. Finally, sources/drains for the PMOS transistor and the NMOS transistor are formed in the substrate, oppositely adjacent to the first gate and the second gate.

REFERENCES:
patent: 5248350 (1993-09-01), Lee
patent: 5877050 (1999-03-01), Gardner et al.
patent: 5885887 (1999-03-01), Hause et al.
patent: 5953614 (1999-09-01), Liu et al.
patent: 5956591 (1999-09-01), Fulford, Jr.
patent: 5994743 (1999-11-01), Masuoka

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