Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-11
2002-12-31
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S165000, C438S241000, C438S258000, C438S981000
Reexamination Certificate
active
06500715
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit (IC) devices configured using metal oxide semiconductor (MOS) transistors, and more particularly to a semiconductor IC device which employs specific MOS transistors with a gate insulation film thin enough to permit flow of tunnel current therein and which is adaptable for use with low-power circuitry operable with low voltages of 2 volts or less.
BACKGROUND ART
One prior known semiconductor integrated circuit device employing highly miniaturized MOS transistors fabricated by microelectronics fabrication technology is disclosed, for example, in a paper entitled “Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation,” 1994 Custom Integrated Circuit Conference (CICC), pp. 267-270. This paper also teaches the correlation of the transistor threshold value versus flow of leakage current during standby periods.
DISCLOSURE OF THE INVENTION
Currently available standard MOS transistors are typically designed to operate with a gate voltage of from 1.8 to 2.5 volts (so-called the “gate-to-source” voltage which is normally equivalent to the power supply voltage) while making use of a gate insulation film ranging from 5 to 6 nanometers (nm) in thickness. Generally, as the integration density of MOS transistors increases, the transistor size decreases, and the thickness of the gate insulation film decreases accordingly. The present inventors Presently predict that MOS-IC devices of the next generation will require use of further miniaturized MOS transistors operable with a gate voltage of 2 volts or less while reducing the thickness of gate insulation film down at 4 nm or less.
Principally, it may be considered that the operation speed of MOS transistors remains inversely proportional to the gate insulation film thickness decreases—that is, as this thickness decreases, the MOS transistor speed increases. However, this does not come without accompanying a “trade-off” penalty: When the MOS gate insulation film becomes too thinner, a tunnel current begins flowing therethrough. This can result in an increase in leakage current (tunnel leakage current), such as a source-to-gate current or drain-to-gate current, which inherently does never take place in standard MOS transistors. Such increase in tunnel leakage current in turn leads to an increase in power dissipation of MOS transistors during standby periods thereof. In the description such dielectric films permitting tunnel current leakage will be referred to as the “thin” gate insulation film; likewise, certain MOS transistors employing such dielectric film will be called the “thin-film” MOS transistors hereinafter. On the contrary, standard MOS transistors in which such tunnel leakage current does not flow will be referred to as the “thick-film” MOS transistors. The “tunnel current leakage” problem has been also discussed in the monthly journal titled “Semiconductor World,” July 1995 at pp. 80-94; unfortunately, this is completely silent about any ideas for solving this problem.
A mechanism of an increase in power dissipation during standby due to tunnel current will be discussed more precisely in conjunction with the graphs shown in FIG.
10
.
See FIG.
10
(
a
). This is a graphical representation showing experimental results concerning the drain voltage versus drain current characteristics of one thick-film MOS transistor. Plotting experimental data in this graph assumes that its gate oxide film measures approximately 6 nm in thickness. Since the oxide film employed herein is thick enough to render negligible the tunnel leakage current which can flow between the gate and source or between the gate and drain.
See FIG.
10
(
b
), which presents the drain-voltage/drain-current characteristics of a thin-film MOS transistor. This assumes that a gate oxide film used is 3.5 nm in thickness. Since the oxide film is thin, leakage current can flow between the gate and source and also between the gate and drain thereof. Accordingly, even where the drain voltage is at zero volts, a non-negligible amount of current flows between the gate and drain when its gate voltage is not zero volts. In the graph of FIG.
10
(
b
), a drain current of 0.5 milliamperes (mA) or more or less was derived when the gate voltage is 2.0 volts.
In complementary MOS (CMOS) circuitry configured using thick-film MOS transistors, since gate leakage current remains negligible in amount, any constant current (DC current) will by no means flow insofar as leakage current is absent between the source and drain. On the contrary, with CMOS circuitry employing thin-film MOS transistors, gate leakage current does flow so that constant current (DC current) flows accordingly. This means that some power dissipation arises even where the circuitry is inoperative.
See
FIG. 11
, which shows the relation of the thickness of gate insulation film versus gate leakage current. Even when the gate voltage is at 2 to 3 volts or around it, if the gate insulation film is 6 nm or greater in thickness, then any resultant tunnel current remains harmless in practical applications. On the other hand, it may be seen by those skilled in the art that even if the gate voltage is potentially decreased to range from 2 to 1.5 volts which may be lower than ever, the leakage current will no longer remain negligible in magnitude once after the thickness of gate insulation film is reduced at approximately 3 nm. Presumably, if the gate voltage is 2 volts or more or less, then the boundary exists at a 4-nm range of gate insulation film thickness or around it. According to the teachings of the Semiconductor World document, it has been pointed out that the tunnel effect in quantum theory takes place with a 5-nm gate insulation film point being as the criticality. This document also teaches that a remarkable tunnel current can occur not only when the gate insulation film is as thin as 1.5 nm but also when it falls within a range of from 3 to 3.5 nm. As can be seen from the graph of
FIG. 11
, while the gate voltage tends to be lowered for reduction in power dissipation; even in this situation, when the gate insulation film becomes thinner to decrease from 2.9 to 2.0 nm in thickness, large leakage current begins flowing even upon application of a gate voltage of 1 volt or below. Additionally, it is currently presumed that a minimal thickness of gate insulation films capable of retaining the nature of silicon oxide is about 10 angstroms.
Another approach is known which suppresses a sub-threshold source-to-drain leakage current by potentially raising the threshold value of MOS transistors. However, even with use of such approach, it stays impossible in principle to reduce standby power dissipation due to the flow of source-to-gate tunnel current.
While the gate leakage current (tunnel current) might be under control by increasing the thickness of gate insulation films to reduce standby power dissipation involved, this does not come without accompanying a penalty: As discussed supra, if such MOS transistors are employed for circuitry then operation speed decreases making it impossible or at least greatly difficult to attain any desired performance.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of reducing standby power dissipation without having to degrading circuit operation speed.
In order to attain the foregoing object, the invention provides a low-power/high-performance semiconductor integrated circuit device by selective use of different kinds of MOS transistors including thick-film MOS transistors and thin-film MOS transistors, wherein the former is negligible in flow of tunnel leakage current whereas the latter is capable of operating at high speeds while accompanying the tunnel current leakage problem.
In accordance with the principles of the invention, there is provided a semiconductor integrated circuit device including on the same substrate a plurality of kinds of MOS transistors different in magnitude of a leakage current flowing either
Horiguchi Masashi
Matsuzaki Nozomu
Mizuno Hiroyuki
Fahmy Wael
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Toledo Fernando
LandOfFree
Method of forming a CMOS structure having gate insulation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a CMOS structure having gate insulation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a CMOS structure having gate insulation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2990143