Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-02
2002-04-16
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S386000, C438S387000, C438S396000, C438S669000, C438S957000
Reexamination Certificate
active
06372574
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to methods of forming capacitor container electrodes and to methods of patterning metal layers.
BACKGROUND OF THE INVENTION
One common goal in capacitor fabrication is to maximize the capacitance for a given size capacitor. It is desirable that stored charge be at a maximum immediately at the physical interface between the respective electrodes or capacitor plates and the capacitor dielectric material between the plates. Typical integrated circuitry capacitors have electrodes or plates which are formed from doped semiconductive material such as polysilicon. The polysilicon is usually heavily doped to impart a desired degree of conductivity for satisfactory capacitor plate operation.
One drawback of heavily doping polysilicon is that during operation a charge depletion region develops at the interface where charge maximization is desired. Hence, a desired level of charge storage is achieved at a location which is displaced from the interface between the capacitor plate and the dielectric material. Another drawback of heavily doped polysilicon capacitor plates is that during processing, some of the dopant can migrate away from the polysilicon and into other substrate structures. Dopant migration can adversely affect the performance of such structures. For example, one type of integrated circuitry which utilizes capacitors are memory cells, and more particularly dynamic random access memory (DRAM) devices. Migratory dopants from doped polysilicon capacitor plates can adversely impact adjacent access transistors by undesirably adjusting the threshold voltages.
As the memory cell density of DRAMs increases there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. The principal way of increasing cell capacitance heretofore has been through cell structure techniques. Such techniques include three dimensional cell capacitors such as trench or stacked capacitors.
Highly integrated memory devices, such as 256 Mbit DRAMs and beyond, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness. Insulating inorganic metal oxide materials, such as Ta
2
O
5
and barium strontium titanate, have high dielectric constants and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. All of these materials incorporate oxygen and are otherwise exposed to oxygen and anneal for densification to produce the desired capacitor dielectric layer. In many of such applications, it will be highly desirable to utilize metal for the capacitor electrodes, thus forming a metal-insulator-metal capacitor. In other applications, it may still be desirable to use polysilicon as part of the capacitor electrode material using a conductive or other diffusion barrier, such as platinum, to avoid formation of insulative oxides of the electrode material.
One method of fabricating a capacitor is in the form of a container. A container forming material, typically borophosphosilicate glass (BPSG), is formed over a substrate. A container opening is formed within the container forming material. A conductive layer is formed to less than completely fill the container opening, thereby forming an upwardly open container-like shape received within the opening and outwardly thereof over the container forming material. Such layer or layers can be then be removed from outwardly of the container opening by polishing or other processes, thereby leaving an isolated conductive container construction within the opening which can be utilized as a capacitor storage electrode. This provides one way of forming a capacitor electrode in a desired shape using a single masking step for forming both the opening and ultimate patterning of individual capacitor electrodes received therein.
Certain materials are, however, extremely challenging to remove by the typical mechanical or chemical-mechanical polishing processes utilized to isolate the electrodes within the container openings. For example, platinum is difficult to polish when used as a lower electrode in a container style capacitor as it tends to “smear” during polish. It would be desirable to develop alternate capacitor fabrication methods which enable this problem to be alleviated. While the invention was motivated from this perspective, it is in no way so limited to addressing or overcoming any aspect of this particular problem, however. Further, while motivated and directed relative to fabrication problems associated with formation of the above-identified capacitor constructions, the invention is further not so limited. The invention is seen to have applicability to any method of patterning a metal layer utilizing any integrated circuit construction. The invention is only limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents, with the specification herein only providing but exemplary preferred embodiments.
SUMMARY
The invention comprises methods of forming a capacitor container electrode and methods of patterning a metal layer. In one implementation, a method of patterning a metal layer includes masking a first portion of a metal layer while leaving a second portion of the metal layer unmasked over a substrate. With the masking in place, the second portion is reacted with silicon to form a metal silicide from the metal layer. The metal silicide is removed from the substrate while substantially leaving the first portion on the substrate. The masking is removed from the substrate.
In one implementation, a method of patterning a metal layer includes depositing and patterning a silicon comprising layer over a substrate. A metal layer is formed over the patterned silicon comprising layer, and includes a portion extending to elevationally inward of the metal layer. Metal of the metal layer is reacted with silicon of the silicon layer to form a metal silicide and leave at least some of the portion unreacted. The metal silicide is removed from the substrate while substantially leaving the unreacted portion of the metal layer on the substrate.
These and other implementations can be used to form capacitor container electrodes and other circuit devices.
REFERENCES:
patent: 5053105 (1991-10-01), Fox, III
patent: 5587338 (1996-12-01), Tseng
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6133129 (2000-10-01), Xiang et al.
patent: 6136659 (2000-10-01), Schindler et al.
Fishburn Fred
Lane Richard H.
Everhart Caridad
Lytle Craig P.
Micro)n Technology, Inc.
Wells St. John P. S.
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