Method of forming a buried-sidewall-strap two transistor one cap

Details Method of forming a buried-sidewall-strap two transistor one cap Method of forming a buried-sidewall-strap two transistor one cap

1996-04-26

1998-07-14

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438239, 438238, 438244, 438253, H01L 218242

Patent

active

057803358

ABSTRACT:
A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

REFERENCES:
patent: 5571743 (1996-11-01), Henkels et al.

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