Method of forming a buried plate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S392000, C438S561000

Reexamination Certificate

active

06316310

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a buried plate, for example, in a semiconductor device, such as, a trench storage capacitor.
When forming a buried plate in a silicon trench, a layer of arsenic doped glass (SiO
2
) is disposed over a lower portion of the side walls of the trench using a Low Pressure Chemical Vapour Deposition (LPCVD) technique. The arsenic doped glass layer, when annealed, results in the diffusion of the arsenic into the silicon trench. However, in order to avoid increasing parasitic leakage currents along side walls of the trench, diffusion of the arsenic needs to be restricted to the lower portion of the trench, thereby avoiding diffusion of arsenic into the whole of the side walls of the silicon trench. It is therefore known to deposit an undoped glass layer over the trench using a Plasma Chemical Vapour Deposition (CVD) technique. The undoped glass layer completely covers the side walls and the arsenic doped glass layer in order to prevent arsenic escaping into the trench and causing an electrical connection which could short-circuit subsequently deposited electrodes. Separate stand-alone pieces of semiconductor processing equipment, sometimes known as tools or chambers, are used to deposit layers using the above-mentioned LPCVD and CVD techniques, respectively.
The above description of the known process has been simplified, and the full process required to achieve the above-described structure has a relatively large number of complex steps.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to simplify the above process and therefore save manufacturing costs.
According to the present invention, there is provided a method of forming a buried plate for a semiconductor trench, comprising the steps of: depositing a first layer comprising a dopant; depositing a second layer of undoped material on the first layer; etching the first and second layers to a predetermined depth; annealing the first and second layers for out-diffusing the dopant onto the semiconductor trench, and removing the first and second layers, wherein the first layer is not exposed to air before the second layer is deposited thereon.
It is thus possible to provide a method of forming a buried plate where the formation of the undoped glass layer is carried out in the same semiconductor tool as that used for the LPCVD of the arsenic doped glass layer, thereby obviating the need for a separate semiconductor tool to carry out CVD of the undoped glass layer. The removal of the step requiring a plasma CVD chamber reduces manufacturing costs considerably, the overall processing time, and improves device performance characteristics.
Preferably, the first layer comprises arsenic doped glass. The second layer may comprise undoped glass.
More preferably, the arsenic doped glass is deposited using Tetra Ethyl Arsenate (TEAS) and undoped glass is deposited using Tetra Ethyl Ortho Silicate (TEOS).
Also, it has been discovered that an upper portion, relative to the bottom of the cavity of the trench, of the first layer may remain exposed after the etching step, without risking arsenic escaping into the trench.
FIGS. 1
to
7
are schematic diagrams of the various stages in the formation of a buried plate in a semiconductor trench constituting an embodiment of the invention;
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.


REFERENCES:
patent: 5618751 (1997-04-01), Golden et al.
patent: 6057216 (2000-05-01), Economikos et al.
patent: 6096598 (2000-08-01), Furukawa et al.
Copy of Search Report from the U.K. Patent Office. No date.

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