Method of forming a buried bitline in a vertical DRAM device

Details Method of forming a buried bitline in a vertical DRAM device Method of forming a buried bitline in a vertical DRAM device

1999-01-28

2001-04-17

Trinh, Michael (Department: 2833)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S246000, C438S563000, C438S561000

Reexamination Certificate

active

06218236

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method of fabricating an outdiffused buried bitline in a n-type vertical dynamic random access memory (DRAM) array. The buried bitline provided by the inventive method is an outdiffused region which has low resistance, high dopant concentration and a shallow penetration depth so as to avoid the floating body effect for such devices.
An n-type semiconductor memory device comprising the outdiffused buried bitline of the present invention is also provided herein.
BACKGROUND OF THE INVENTION
As semiconductor memory devices such as n-type DRAMs are being scaled down in dimensions, there is a continuous need to maintain a sufficiently high storage charge per capacitor unit area. In order to construct high density semiconductor memory devices in a reasonable sized chip area, the cell structures have changed from planar-type capacitors to either trench or stacked capacitors.
All efforts to increase capacitance without increasing planar area can be categorized into building three dimensional capacitor structures. Some examples of three dimensions capacitor structures existing in the art are trench capacitors and stacked capacitors. While solving the above problem of planar capacitors, trench capacitors and stacked capacitors have their own problems which limit their use and/or reliability.
One major problem associated with trench capacitors is that when the semiconductor memory device is beyond 16 Mbit the trench forming the capacitor region needs to be very deep. Technical problems and even theorized physical limitations in processing deep trenches are known. When the stacked capacitor approach is used to fabricate high density DRAMs, very complicated stacked capacitors are needed, such as fin structures and crown capacitors.
In recent years, in order to obtain denser arrays, smaller sized cells are required. This has led to trench capacitor devices wherein the transfer device is formed on a pillar below or above the capacitor. One major problem with these types of prior art trench capacitors is that the transfer device body is isolated from the substrate of the device. In other words, the body of the pillar (transfer device) is not continuous with the underlying substrate. The term “continuous” is used herein to denote that the middle region of the vertical transistor region is composed of the same material as the underlying substrate and thus in direct contact with the underlying substrate.
This isolation results in the device exhibiting the so-called floating body effect. As is known to those skilled in the art, devices that contain a floating body exhibit a higher degree of leakage than devices which do not have a floating body. This high degree of leakage results in decreased retention times for such devices; therefore such devices have limited use.
The above effects are created since prior art methods are unable to fabricate an outdiffused shallow junction region exhibiting the lowest possible resistance at the highest concentration of dopant material. In the prior art, a one step rapid thermal annealing (RTA) process is employed to form the outdiffused regions. While the prior art one step RTA is capable of forming a shallow penetration depth, it does not form an outdiffused region having the lowest possible resistance at the highest possible dopant concentration level. The formation of outdiffused shallow regions exhibiting the lowest possible resistance at the highest dopant concentration is of great importance in forming an outdiffused bitline structure having a continuous body.
In view of the above drawbacks with prior art methods, there is a continued need to develop new and improved methods of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device which avoids the floating body effect observed with prior art vertical semiconductor memory devices, yet is capable of exhibiting the lowest possible resistance at the highest dopant concentration possible.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a buried bitline in a vertical semiconductor memory device such as a n-type array DRAM which eliminates the floating body effect observed with prior art vertical semiconductor memory devices.
Another object of the present invention is to fabricate a shallow outdiffused buried bitline that exhibits the lowest resistance (less than about 5 ohms/sq.) at the highest possible dopant concentration (greater than 5×10
19
/cm
2
).
These and other objects and advantages are achieved in the present invention by utilizing the inventive method wherein annealing and oxidation are carried out in two separate, distinct steps so as to achieve a high dopant concentration near the semiconducting surface of the pillar structure and to keep the dopant within less than 0.1 micrometers laterally from the semiconducting surface. It is emphasized that the prior art one step RTA is incapable of forming a shallow outdiffused region which has the lowest possible resistance at the highest possible dopant concentration level.
In one embodiment, the present invention provides a method of fabricating a shallow outdiffused buried bitline having a low resistance and a high dopant concentration in a vertical semiconductor memory device comprising the steps of:
(a) providing a structure having a dielectric layer on at least one surface of a p-type semiconducting material;
(b) forming pillar regions in said structure provided in (a) by etching trenches in said structure;
(c) forming a recessed liner in said trenches, wherein said recessed liner is composed of arsenic (As) or phosphorous (P) doped glass;
(d) forming a first oxide layer over the structure provided in (c);
(e) annealing the structure so as to diffuse, i.e. drive-in, said As or P from said recessed liner into said p-type semiconducting material and said pillar regions;
(f) optionally removing said first oxide layer and any recessed liner material remaining in said trenches;
(g) oxidizing the structure provided in (e) or (f) so as to form a second oxide layer lining said pillars and to cause pile-up of said dopant material in a region underlying said second oxide layer;
(h) removing said second oxide layer and optionally said first oxide layer and said recessed liner from said trenches; and
(i) etching said p-type semiconducting material in said trenches so as to provide separate shallow outdiffused buried bitlines in said pillar regions, wherein said outdiffused buried bitlines extend from the pillars' sidewalls.
By annealing and oxidizing the structure in two distinct processing steps and at two distinct temperature ranges rather than one, the following occur: First, the annealing step, which is carried out at high temperatures (greater than 950° C.), drives As or P into the p-type semiconducting material and the separate oxidization step, which is carried out at lower temperatures than the annealing step (less than 950° C.), causes a snow-plow effect piling-up As or P in a region below the second oxide layer formed during oxidation. It should be noted that the low temperature oxidation step does not cause any drive-in of the dopant material, yet it is capable of forming a shallow junction having low resistance and a high dopant concentration.
In an optional embodiment of the present invention, the pillar regions formed in step (b) above are designed to have a starting dimension which is larger than the final desired dimension of the pillars. This embodiment takes into account that the oxidization step may result in some loss of the size of the pillar.
Another aspect of the present invention relates to a vertical semiconductor memory device which comprises a p-type semiconducting material; an array of cells having pillars formed on said p-type semiconducting material, said pillars being arranged in rows and columns, each of said pillars having an upper region doped with a n-type of impurity, a middle region doped with a p-

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