Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-16
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S250000, C438S393000
Reexamination Certificate
active
06372570
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuit manufacturing, and more specifically, to the manufacturing of capacitors adapted to operating at high frequency (above one gigahertz), that is, having a small access resistance and a small stray capacitance with substrate elements.
2. Discussion of the Related Art
An integrated circuit includes several layers and regions of different doping levels formed in a semiconductor substrate, currently silicon. Generally, especially in MOS-type technologies, one, or sometimes several, polysilicon level(s) is (are) provided, to form, in particular, the gate(s) of MOS transistors or of memory points. Several metallization levels are provided to ensure the interconnections.
Each formation of a conductive layer, be it doped polysilicon or metal, is followed by the deposition of at least one insulating layer so that, at-the locations where this is desired, the next conductive layer can be insulated from the underlying layer.
Thus, it is possible to form a capacitor each time there are two successively deposited conductive layers separated by an insulating layer.
To form capacitors capable of operating at high frequency, with a small access resistance and a small stray capacitance with elements of the semiconductor component, the use of capacitors having one plate formed of a semiconductive region, as well as the use of capacitors having one plate made of polysilicon has to be avoided. Indeed, both cases provide relatively high access resistances and a relatively/strong capacitive coupling with elements of the semiconductor substrate. Capacitors between metallizations which are more distant from the substrate and for which the access resistance is small thus have to be used, since metallizations generally conduct better than doped single-crystal silicon or polysilicon.
However, practically all known capacitors between metallization levels have various drawbacks. Often, the second metal is etched while a thin insulator layer has been deposited. As a result, upon etching of the metal, the thin insulator can be damaged, which risks embrittling it and causing punctures. In many solutions, several masking and etching steps have to be provided in addition to those existing in a conventional method. There also are problems of reliability at the level of the capacitor sides. Further, in the case where aluminum is used for one of the metals, there appear problems due to the point punch-through of the aluminum into the neighboring layers.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a method of manufacturing a capacitor between metallization levels which avoids one or several of the above-mentioned disadvantages.
A more specific object of the present invention is to provide such a method which is compatible with conventional lines of CMOS component manufacturing.
Another object of the present invention is to provide such a method which, practically, does not add any step to the normal steps of CMOS-type component manufacturing.
To achieve these and other objects, the present invention provides a method of manufacturing a capacitor including the steps of depositing a first metal level and etching this first metal level to leave in place at least one region corresponding to a first plate of a capacitor and at least one contact area corresponding to a connection with which an upper contact is desired to be established; depositing an insulating layer between metallization levels; forming a first opening above the first capacitor plate; depositing a thin insulating layer; forming a second opening above the contact area; depositing a second metal level to completely fill up the second opening; performing a physico-chemical etching to remove the second metal layer outside regions where it fills up the openings; depositing a third metal level and leaving in place portions of this third metal level above the capacitor region and the contact region.
According to an embodiment of the present invention, the first and second metal levels are in tungsten.
According to an embodiment of the present invention, the first opening is made to have slanted sides while the second opening is made to have steep sides.
REFERENCES:
patent: 5563762 (1996-10-01), Leung et al.
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patent: 6100195 (2000-08-01), Chan et al.
patent: 6242315 (2001-06-01), Lin et al.
patent: WO 98/05071 (1998-02-01), None
French Search Report from French Patent Application No. 98 09437, filed Jul. 21, 1998.
Patent Abstracts of Japan, vol. 018, No. 171 (E-1529), Mar. 23, 1994 & JP-A-05 343613 (Yamaha Corp.).
Banvillet Henri
Gris Yvon
Guelen Jos
Lunardi Geneviève
Maddalon Catherine
Bowers Charles
Galanthay Theodore E.
Huynh Yennhu B.
Morris James H.
STMicroelectronics S. A.
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