Method of flash cell formation

Details Method of flash cell formation Method of flash cell formation

2001-11-13

2002-10-01

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S594000

Reexamination Certificate

active

06458660

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of memory cell formation, and more particularly to a method of forming a memory cell having buried diffusion oxide.
2. Description of the Related Art
Electrically erasable and programmable read only memory (EEPROM) is currently one the most widely used memory devices applied in personal computers and electronic equipment. A memory cell in a early developed conventional EEPROM comprises a transistor with a floating gate to achieve the operations of writing, erasing, and storing data while electrical shut down. This conventional memory cell typically occupies a large surface area and the data access speed is between 150 sn to 200 sn. A lately developed memory cell having a faster data access speed ranged between 70 sn to 80 sn is known as a flash memory. While storing data, a high voltage of 8V is applied between the drain region and the source region. Meanwhile, the controlling gate is biased with the same high voltage. The hot electrons thus flow out of the source region and toward the drain region. While approaching the drain region, these hot electrons tunnel through the oxide layer and are trapped in the floating gate. This is known as the drain side injection operation. By applying a positive voltage to the source region and a negative voltage to the controlling gate, the electrons trapped in the floating gate flow out of the floating gate and tunnel through the oxide layer. Thus the stored data are erased and the floating gate is retrieved to the status before data storing.
FIG. 1A
shows a cross-sectional view of a cell region and a periphery region amid a conventional flash cell formation process. A tunnel oxide layer
101
, a polysilicon layer
102
and a silicon nitride layer
104
are formed on a silicon substrate
100
. Trenches are formed in the polysilicon layer
102
and the silicon nitride layer
104
and filled with a silicon dioxide layer
106
. The silicon dioxide layer
106
having the profile shown in
FIG. 1A
is formed by using a high density plasma (HDP) chemical vapor deposition (CVD) process.
FIG. 1B
shows a result of etching the silicon dioxide layer
106
. The portion of silicon dioxide layer
106
on the cell region is etched to form buried diffusion oxide.
FIG. 1C
shows a result of forming a photoresist layer
108
over the cell region and removing the portion of silicon dioxide layer
106
on the periphery region. In the following process steps, as shown in
FIG. 1D
, the photoresist layer
108
and the portion of the silicon nitride layer
104
are sequentially removed, and a polysilicon layer(not shown)is then formed over the substrate
100
. The use of the silicon nitride layer
104
of the flash cell formation process set forth renders the flash cell formation process more complicated and time-consuming. Additional photolithography and etching processes are thus necessary and the conventional flash cell formation process mentioned above obviously will not meet the requirements of modern integrated circuit process.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The advantages of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of forming a memory cell having buried diffusion oxide.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method of forming a memory cell having buried diffusion oxide, the method comprises the steps of providing a substrate having a tunnel oxide layer and a first conductive layer thereon, forming trenches into said tunnel oxide layer and said first conductive layer to expose said substrate, filling said trenches with a dielectric material to a predetermined thickness, removing a portion of said first conductive layer to form a surface lower than said predetermined thickness; and forming a second conductive layer over said dielectric material and said first conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5696019 (1997-12-01), Chang
patent: 6037251 (2000-03-01), Tu et al.
patent: 6177317 (2001-01-01), Huang et al.

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